Editing Logic family (section)

==PMOS and NMOS logic==
{{Main|PMOS logic|NMOS logic}}
{{See|MOSFET|Depletion-load NMOS logic}}

[[PMOS logic|P-type MOS (PMOS) logic]] uses [[p-channel]] [[MOSFET]]s to implement [[logic gate]]s and other [[digital circuit]]s. PMOS logic dominated industry approximately from 1960 to 1970.

[[NMOS logic|N-type MOS (NMOS) logic]] uses [[n-channel]] MOSFETs to implement logic gates and other digital circuits.

For devices of equal current driving capability, n-channel MOSFETs can be made smaller than p-channel MOSFETs, due to p-channel charge carriers ([[electron hole|holes]]) having lower [[electron mobility|mobility]] than do n-channel charge carriers ([[electrons]]); also, producing only one type of MOSFET on a silicon substrate is cheaper and technically simpler. These were the driving principles in the design of [[NMOS logic]], which uses n-channel MOSFETs exclusively. However, neglecting [[leakage current]], NMOS logic consumes power even when no switching is taking place, unlike CMOS logic.

The MOSFET invented at Bell Labs between 1955 and 1960 had both pMOS and nMOS devices with a [[20&nbsp;μm process]].<ref name=":0">{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208|url-access=subscription }}</ref><ref>{{Cite journal |last1=Frosch |first1=C. J. |last2=Derick |first2=L |date=1957 |title=Surface Protection and Selective Masking during Diffusion in Silicon |url=https://iopscience.iop.org/article/10.1149/1.2428650 |journal=Journal of the Electrochemical Society |language=en |volume=104 |issue=9 |pages=547 |doi=10.1149/1.2428650|url-access=subscription }}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref><ref name="Lojek1202">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=9783540342588 |page=120}}</ref><ref name="Lojek">{{cite book |last1=Lojek |first1=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer |isbn=9783540342588 |pages=321–3}}</ref> Their original MOSFET devices had a gate length of 20{{nbsp}}[[μm]] and a [[gate oxide]] thickness of [[100 nm]].<ref>{{cite book |last1=Sze |first1=Simon M. |author1-link=Simon Sze |title=Semiconductor Devices: Physics and Technology |date=2002 |publisher=Wiley |isbn=0-471-33372-7 |page=4 |edition=2nd |url=http://www.fulviofrisone.com/attachments/article/453/Semiconductor.Devices_Physics.Technology_Sze.2ndEd_Wiley_2002.pdf}}</ref> However, the nMOS devices were impractical, and only the pMOS type were practical working devices.<ref name="Lojek"/> A more practical NMOS process was developed several years later. NMOS was initially faster than [[CMOS]], thus NMOS was more widely used for computers in the 1970s.<ref name="shmj">{{cite web |title=1978: Double-well fast CMOS SRAM (Hitachi) |url=http://www.shmj.or.jp/english/pdf/ic/exhibi727E.pdf |website=Semiconductor History Museum of Japan |date=23 January 2019 |access-date=5 July 2019}}</ref>

With advances in technology, CMOS logic displaced NMOS logic in the mid-1980s to become the preferred process for digital chips.