Editing Logical effort (section)

===Minimum delay===
It can be shown that in multistage logic networks, the minimum possible delay along a particular path can be achieved by designing the circuit such that the stage efforts are equal.  For a given combination of gates and a known load, ''B'', ''G'', and ''H'' are all fixed causing ''F'' to be fixed; hence the individual gates should be sized such that the individual stage efforts are
:<math>f = F^{1/N}</math>
where ''N'' is the number of stages in the circuit.