Editing Magnetic-core memory (section)

===Production economics===
In 1953, tested but not-yet-strung cores cost {{USD|0.33}} each.  As manufacturing volume increased, by 1970 IBM was producing 20 billion cores per year, and the price per core fell to {{USD|0.0003}}.  Core sizes shrank over the same period from around {{convert|0.1|inch|mm|abbr=out}} diameter in the 1950s to {{convert|0.013|inch|mm}} in 1966.<ref>{{harvnb|Pugh|Johnson|Palmer|1991|pp=[https://archive.org/details/ibms360early370s0000pugh/page/204 204–6]}}</ref>  The power required to flip the magnetization of one core is proportional to the volume, so this represents a drop in power consumption by a factor of 125.

The cost of complete core memory systems was dominated by the cost of stringing the wires through the cores.  Forrester's coincident-current system required one of the wires to be run at 45 degrees to the cores, which proved difficult to wire by machine, so that core arrays had to be assembled under microscopes by workers with fine motor control.

In 1956, a group at IBM filed for a patent on a machine to automatically thread the first few wires through each core.  This machine held the full plane of cores in a "nest" and then pushed an array of hollow needles through the cores to guide the wires.<ref>Walter P. Shaw and Roderick W. Link, Method and Apparatus for Threading Perforated Articles, {{US patent|2958126}}, granted Nov. 1, 1960.</ref>  Use of this machine reduced the time taken to thread the straight X and Y select lines from 25 hours to 12 minutes on a 128 by 128 core array.<ref>{{cite book |title=IBM's Early Computers |first1=Charles J. |last1=Bashe |first2=Lyle R. |last2=Johnson |first3=John H. |last3=Palmer |publisher=MIT Press |location=Cambridge, MA |year=1986 |pages=268 |isbn=0-262-52393-0}}</ref>

Smaller cores made the use of hollow needles impractical, but there were numerous advances in semi-automatic core threading.  Support nests with guide channels were developed. Cores were permanently bonded to a backing sheet "patch" that supported them during manufacture and later use. Threading needles were [[Butt welding|butt welded]] to the wires, the needle and wire diameters were the same, and efforts were made to eliminate the use of needles.<ref>Robert L. Judge, Wire Threading Method and Apparatus, {{US patent|3314131}}, granted Apr. 18, 1967.</ref><ref>Ronald A. Beck and Dennis L. Breu, Core Patch Stringing Method, {{US patent|3872581}}, granted Mar. 25, 1975.</ref>

The most important change, from the point of view of automation, was the combination of the sense and inhibit wires, eliminating the need for a circuitous diagonal sense wire.  With small changes in layout, this also allowed much tighter packing of the cores in each patch.<ref name=US3329940>Creighton D. Barnes, et al., Magnetic core storage device having a single winding for both the sensing and inhibit function, {{US patent|3329940}}, granted 4 July 1967.</ref><ref name=US3711839>Victor L. Sell and Syed Alvi, High Density Core Memory Matrix, {{US patent|3711839}}, granted Jan. 16, 1973.</ref>

By the early 1960s, the cost of core fell to the point that it became nearly universal as [[main memory]], replacing both inexpensive low-performance [[drum memory]] and costly high-performance systems using [[vacuum tube]]s, and later discrete [[transistor]]s as memory. The cost of core memory declined sharply over the lifetime of the technology: costs began at roughly {{USD|1.00}} per bit and dropped to roughly {{USD|0.01}} per bit.

Core memory was made [[obsolete]] by [[semiconductor memory|semiconductor]] [[integrated circuit]] memories in the 1970s, though remained in use for mission-critical and high-reliability applications in the [[IBM System/4 Pi#AP-101|IBM System/4 Pi AP-101]] (used in the [[Space Shuttle]] until an upgrade in early 1990s, and the [[B-52]] and [[B-1B]] bombers).<ref>{{Cite web |title=Project History: Magnetic Core Memory |url=https://web.mit.edu/6.933/www/core.html |access-date=2023-07-14 |website=web.mit.edu |archive-url=https://web.archive.org/web/20230714195033/https://web.mit.edu/6.933/www/core.html |archive-date=2023-07-14 |url-status=dead}}</ref><ref>{{Citation |author=Norman, P. Glenn |title=The new AP101S General-Purpose Computer (GPC) for the Space Shuttle |journal=IEEE Proceedings |volume=75 |issue=3 |pages=308–319 |year=1987 |bibcode=1987IEEEP..75..308N |doi=10.1109/PROC.1987.13738 |s2cid=19179436}}</ref><ref>{{cite book |last1=Stormont |first1=D.P. |last2=Welgan |first2=R. |title=Proceedings of National Aerospace and Electronics Conference (NAECON'94) |chapter=Risk management for the B-1B computer upgrade |date=23–27 May 1994 |chapter-url=https://zenodo.org/record/1232223 |volume=2 |pages=1143–1149 |doi=10.1109/NAECON.1994.332913 |isbn=0-7803-1893-5 |s2cid=109575632}}<!--|access-date=23 October 2013--></ref>

An example of the scale, economics, and technology of core memory in the 1960s was the 256K 36-bit word (1.2&nbsp;[[MiB]]<ref>Internally, the Moby Memory had 40 bits per word, but they were not exposed to the PDP-10 processor.</ref>) core memory unit installed on the [[PDP-6]] at the [[MIT Computer Science and Artificial Intelligence Laboratory|MIT Artificial Intelligence Laboratory]] by 1967.<ref>{{cite report |url=https://apps.dtic.mil/dtic/tr/fulltext/u2/681342.pdf |archive-url=https://web.archive.org/web/20210508105745/https://apps.dtic.mil/dtic/tr/fulltext/u2/681342.pdf |url-status=dead |archive-date=8 May 2021 |publisher=Massachusetts Institute of Technology |title=Project MAC. Progress Report IV. July 1966-July 1967 |page=18 |id=681342 |access-date=2020-12-07}}</ref> This was considered "unimaginably huge" at the time, and nicknamed the "Moby Memory".<ref>[[Eric S. Raymond]], [[Guy L. Steele]], ''The New Hacker's Dictionary'', 3rd edition, 1996, {{isbn|0262680920}}, based on the [[Jargon File]], ''s.v.'' 'moby', p. 307</ref> It cost $380,000 ($0.04/bit) and its width, height and depth was {{cvt|69|x|50|x|25|in|cm|0|order=flip}} with its supporting circuitry (189 kilobits/cubic foot = 6.7 kilobits/litre). Its cycle time was 2.75&nbsp;μs.<ref>{{cite book |url=https://www.computerhistory.org/collections/catalog/102731715 |title=FABRI-TEK Mass Core 'Moby' Memory |website=Computer History Museum |date=4 August 1967 |location=US |id=102731715 |access-date=2020-12-07}}</ref><ref>{{cite web |url=http://ljkrakauer.com/LJK/60s/moby.htm |title=Moby Memory  |first=Lawrence J. |last=Krakauer |access-date=2020-12-07}}</ref><ref>Steven Levy, ''Hackers: Heroes of the Computer Revolution'', 2010 (25th anniversary edition), {{isbn|1449393748}}, p. 98</ref>

In 1980, the price of a 16&nbsp;kW ([[kiloword]], equivalent to 32&nbsp;kB) core memory board that fitted into a DEC Q-bus computer was around {{USD|3,000}}. At that time, core array and supporting electronics could fit on a single printed circuit board about {{cvt|25|x|20|cm|in|0}} in size, the core array was mounted a few mm above the PCB and was protected with a metal or plastic plate.{{cn|date=July 2024}}