Editing Memory segmentation (section)

==History==
The [[Burroughs Corporation]] [[Burroughs large systems|B5000]] computer was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory"<ref>{{cite web |last=Mayer |first=Alastair J. W. |title=The Architecture of the Burroughs B5000 - 20 Years Later and Still Ahead of the Times? |url=http://www.smecc.org/The%20Architecture%20%20of%20the%20Burroughs%20B-5000.htm |access-date=2012-03-15}}</ref> based on segmentation. The B5000 is equipped with a segment information table called the Program Reference Table (PRT) which is used to indicate whether the corresponding segment resides in the main memory, to maintain the [[base address]] and the size of the segment.<ref>{{cite book |title=Computer Architecture and Organization |last=Hayes |first=John P. |isbn=0-07-027363-4 |year=1978 |page=371|publisher=McGraw-Hill }}</ref> The later [[Burroughs large systems#B6500|B6500]] computer also implemented segmentation; a version of its architecture is still in use today on the Unisys ClearPath Libra servers.{{Citation needed|date=April 2024}}

The [[GE 645]] computer, a modification of the [[GE-600 series|GE-635]] with segmentation and paging support added, was designed in 1964 to support [[Multics]].

The [[Intel iAPX 432]],<ref>{{cite book |publisher=Intel Corporation |title=Introduction to the IAPX 432 Architecture |date=1981 |pages=78 |url=http://bitsavers.org/components/intel/iAPX_432/171821-001_Introduction_to_the_iAPX_432_Architecture_Aug81.pdf}}</ref> begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor.

The 960MX version of the [[Intel i960]] processors supported load and store instructions with the source or destination being an "access descriptor" for an object, and an offset into the object, with the access descriptor being in a 32-bit register and with the offset computed from a base offset in the next register and from an additional offset and, optionally, an index register specified in the instruction. An access descriptor contains permission bits and a 26-bit object index; the object index is an index into a table of object descriptors, giving an object type, an object length, and a physical address for the object's data, a page table for the object, or the top-level page table for a two-level page table for the object, depending on the object type.<ref>{{cite book |url=http://bitsavers.org/pdf/biin/BiiN_CPU_Architecture_Reference_Man_Jul88.pdf |title=BiiN CPU Architecture Reference Manual |date=July 1998 |publisher=BiiN}}</ref>

[[Prime Computer|Prime]], [[Stratus Technologies|Stratus]], [[Apollo Computer|Apollo]], [[IBM System/38]], and [[IBM AS/400]] (including [[IBM i]]) computers use memory segmentation.