Editing Nascom (section)

==Hardware==
[[File:Nascom1.jpg|thumb|alt=Top-side of assembled Nascom 1 computer|Assembled Nascom 1 computer]]

The Nascom 1<ref>{{cite web|url=http://www.nascomhomepage.com/pdf/NASCOM1.PDF |archive-url=https://web.archive.org/web/20020622194319/http://www.nascomhomepage.com/pdf/NASCOM1.PDF |archive-date=2002-06-22 |url-status=live|title=Nascom 1 Schematics|date=April 1978|website=The Nascom Home Page}}</ref> and Nascom 2<ref>{{cite web|url=http://www.nascomhomepage.com/pdf/Nascom2.pdf |archive-url=https://web.archive.org/web/20030801093113/http://www.nascomhomepage.com/pdf/Nascom2.pdf |archive-date=2003-08-01 |url-status=live|title=Nascom 2 schematics|date=16 June 1979|website=The Nascom Home Page}}</ref> hardware designs had these features in common:

* A 16&nbsp;MHz crystal biased into oscillation and then divided down to create the clocks for the [[CPU]], the serial communications and the video interface
* A Z80/Z80A CPU
* A Z80/Z80A [[Programmed input–output|PIO]]
* A Harris 6402 [[UART]] (or equivalent) that could be used either to communicate with a serial device (e.g. RS232 terminal or printer) or to save and load data using a domestic compact [[cassette recorder]].
* A memory-mapped video display and a [[UHF]] video modulator capable of driving a domestic TV
* Circuitry decoded on IO port 0 to control a software-scanned keyboard, to drive a LED ("DRIVE") and to generate a timed non-maskable interrupt (NMI) that was used to provide a hardware single-step capability
* An LED ("HALT") on the Z80-CPU "/HALT" output, to provide a visual indication that the CPU was halted.

The I/O address map was common between the Nascom 1 and Nascom 2 designs, and the memory address map of the Nascom 2 was a superset of the Nascom 1 memory address map; this allowed a high degree of software compatibility  between the two machines.

The Nascom 1 was implemented entirely using off-the-shelf [[Integrated circuit|integrated-circuits]] and other [[electronic component]]s. The Nascom 2 used 4, 16-pin  [[Bipolar transistor biasing|bipolar]] [[Programmable read-only memory|PROMs]] which acted as [[glue logic]] for decode functions ("N2MD" for memory decode, "N2IO" for I/O decode, "N2V" for video decode and N2DB" for data bus buffer control).

The Nascom 2 had these additional features that were not present on the Nascom 1:

* Power-on reset with timing control to reset the CPU without interrupting the periodic refresh cycles produced by the Z80
* Gating to reset the Z80-PIO (the Z80-PIO has no dedicated reset input)
* A reset-jump circuit that allowed the Z80-CPU to start execution from any 4-Kbyte boundary after reset (the Z80-CPU usually fetches from address 0 after reset). This allowed, for example, control to be passed straight to the BASIC interpreter after reset.
* Microsoft BASIC in an 8Kbyte ROM.
* Two groups of 4 uncommitted 24-pin [[Dual in-line package|DIL]] sockets. Each group could be configured to accommodate 1Kx8 ROM or RAM devices and decoded at a start address of 0x1000, 0x2000, 0xB000, 0xC000 or 0xD000. 
* A 24-pin [[Dual in-line package|DIL]] socket that could accommodate a second [[Character generator|character-generator]] ROM
* Full buffering of the CPU address, data and control to generate the "NAS-BUS" expansion bus.

The Nascom 1 used DIL sockets for making external connections. The photo shows 4 sockets, used for keyboard, serial (cassette and/or teletype/printer), PIO port A, PIO port B. The small "daughterboard" is a home-made implementation of the "snow plough" circuit referred to below.

The I/O address map was decoded as follows:
{| class="wikitable"
|+
!I/O Port address
!Function
|-
|0x0 (read)
|Read keyboard state
|-
|0x0 (write)
|Control keyboard, control single-step (NMI) logic, control "DRIVE" LED
|-
|0x1
|UART Data
|-
|0x2
|UART Control/Status
|-
|0x3
|Unused
|-
|0x4
|Z80-PIO Data Port A
|-
|0x5
|Z80-PIO Data Port B
|-
|0x6
|Z80-PIO Control Port A
|-
|0x7
|Z80-PIO Control Port B
|}
On an unexpanded system, these 8 ports were repeated through the whole of the I/O address space. On an expanded system, the bus signal /NASIO allowed control of the I/O address space.

The memory address map was decoded as follows:
{| class="wikitable"
|+
!Address
!Nascom 1
!Nascom 2
|-
|0x0000-0x07FF
|Monitor (NASBUG, T4, NAS-SYS1, NAS-SYS3)
1 or 2 1Kbyte 2708 EPROM
|Monitor (NAS-SYS1 or NAS-SYS3)
2Kbyte ROM or 2716 EPROM
|-
|0x0800-0x0BFF
|Video RAM
|Video RAM
|-
|0x0C00-0x0FFF
|Workspace RAM
|Workspace RAM
|-
|0x1000-0x1FFF
|
|Decoded on board. Usually used for RAM (4, 1Kbyte devices)
|-
|0x2000-0x2FFF
|
|Decoded on board. Usually used for RAM (4, 1Kbyte devices)
|-
|0xB000-0xBFFF
|
|Decoded on board. Usually used for EPROM (4, 1Kbyte 2708 devices)
|-
|0xC000-0xCFFF
|
|Decoded on board. Usually used for EPROM (4, 1Kbyte 2708 devices)
|-
|0xD000-0xDFFF
|
|Decoded on board. Usually used for EPROM (4, 1Kbyte 2708 devices)
|-
|0xE000-0xFFFF
|
|Microsoft 8Kbyte ROM BASIC
|}