Editing National Semiconductor SC/MP (section)

===Interrupt handling===
The system includes automatic handling of interrupts on the Sense A line. When an interrupt is received and IE is high (enabled), before starting to fetch the next instruction the system instead clears IE to prevent another interrupt, and then exchanges the values in PC and PS3. This has the effect of saving the return address in PR3 and sending the next instruction into the interrupt handler entry point previously stored in PR3.{{sfn|Osborne|Kane|1981|p=3.14}}

The system does not include the equivalent of a return-from-interrupt. This can be performed with another XPPC, copying the previously-saved address in PR3 back to the PC and execution continues where it left off. However, this leaves the wrong address in PR3, not the start of the interrupt handler, but the end. To address this, the common solution is to place the XPPC that returns to the main code one instruction above the handler entry point, rather than at the end. When the handler completes, it jumps back to this instruction, so when XPPC is called, the PC is pointed one location before the proper entry point. Because the system increments the PC before calling an instruction, this means the next interrupt will result it in entering at the correct entry point. This "exit handler" normally also resets the IE to 1 to re-enable interrupts.{{sfn|Osborne|Kane|1981|p=3.16}}