Editing NetBurst (section)

=== Hyper-Pipelined Technology ===
The Willamette and Northwood cores contain a 20-stage [[instruction pipelining|instruction pipeline]]. This is a significant increase in the number of stages compared to the Pentium III, which had only 10 stages in its pipeline. The Prescott core increased the length of the pipeline to 31 stages. A drawback of longer pipelines is the increase in the number of stages that need to be traced back in the event of a branch misprediction, increasing the penalty of said misprediction. To address this issue, Intel devised the Rapid Execution Engine and has invested a great deal into its branch prediction technology, which Intel claims reduces [[branch misprediction]]s by 33% over [[Pentium III]].<ref>{{cite web|date=November 20, 2000|title=The Trace Cache Branch Prediction Unit|url=https://www.tomshardware.com/reviews/intel,264-8.html|access-date=April 30, 2021|work=Intel's New Pentium 4 Processor|publisher=[[Tom's Hardware]]}}</ref> In reality, the longer pipeline resulted in reduced efficiency through a lower number of [[instructions per cycle|instructions per clock]] (IPC) executed as high enough clock speeds were not able to be reached to offset lost performance due to larger than expected increase in power consumption and heat.