Editing PIC microcontrollers (section)

==Device families==
PIC micro chips are designed with a [[Harvard architecture]], and are offered in various device families. The baseline and mid-range families use 8-bit wide data memory, and the high-end families use 16-bit data memory. The latest series, PIC32MZ, is a 32-bit [[MIPS instruction set|MIPS]]-based microcontroller. Instruction word sizes are [[12-bit computing|12 bits]] (PIC10 and PIC12), [[14-bit computing|14 bits]] (PIC16) and [[24-bit computing|24 bits]] (PIC24 and dsPIC). The binary representations of the machine instructions vary by family and are shown in [[PIC instruction listings]].

Within these families, devices may be designated PICnnCxxx (CMOS) or PICnnFxxx (Flash). "C" devices are generally classified as "Not suitable for new development" (not actively promoted by Microchip). The program memory of "C" devices is variously described as OTP, ROM, or EEPROM. As of October 2016, the only OTP product classified as "In production" is the pic16HV540. "C" devices with quartz windows (for UV erasure) are in general no longer available.

===PIC10 and PIC12===
{{Further|topic=this family of microcontrollers|PIC instruction listings#Baseline core devices (12-bit)}}
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.

Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.

Because of the very limited register space (5 bits), 4 rarely read registers were not assigned addresses, but written by special instructions (<code>OPTION</code> and <code>TRIS</code>).

The ROM address space is 512 and may only specify addresses in the first half of each 512-word page. That is, the CALL instruction specifies the low 9 bits of the address, but only the low 8 bits of that address are a parameter of the instruction, while the 9th bit (bit 8) is implicitly specified as 0 by the CALL instruction itself.

Lookup tables are implemented using a computed <code>GOTO</code> (assignment to PCL register) into a table of <code>RETLW</code> instructions. RETLW performs a subroutine return and simultaneously loads the W register with an 8-bit immediate constant that is part of the instruction.

This "baseline core" does ''not'' support [[interrupt]]s; all [[Input/output|I/O]] must be [[Polling (computer science)|polled]]. There are some "enhanced baseline" variants with interrupt support and a four-level call stack.

PIC10F32x devices feature a mid-range 14-bit wide code memory of 256 or 512 words, a 64-byte SRAM register file, and an 8-level deep hardware stack. These devices are available in 6-pin SMD and 8-pin DIP packages (with two pins unused). One input only and three I/O pins are available. A complex set of interrupts are available. Clocks are an internal calibrated high-frequency oscillator of 16&nbsp;MHz with a choice of selectable speeds via software and a 31&nbsp;kHz low-power source.

===PIC16===
{{Further|topic=this family of microcontrollers|PIC instruction listings#Mid-range core devices (14 bit)|PIC instruction listings#Enhanced mid-range core devices (14 bit)}}
[[File:AST Research Ascentia A Series - Synaptics TM1202SPU-154-5 - Microchip PIC16C58A-93300.jpg|thumb|Microchip PIC16C58A]]
[[File:PIC16LF870 in SOIC Socket.jpg|thumb|PIC16LF870 in SOIC Socket]]
These devices feature a 14-bit wide code memory, and an improved 8-level deep call stack. The instruction set differs very little from the baseline devices, but the two additional opcode bits allow 128 registers and 2048 words of code to be directly addressed. There are a few additional miscellaneous instructions, and two additional 8-bit literal instructions, add and subtract. The mid-range core is available in the majority of devices labeled PIC12 and PIC16.

The first 32 bytes of the register space are allocated to special-purpose registers; the remaining 96 bytes are used for general-purpose RAM. If banked RAM is used, the high 16 registers (0x70–0x7F) are global, as are a few of the most important special-purpose registers, including the STATUS register, which holds the RAM bank select bits. (The other global registers are FSR and INDF, the low 8 bits of the program counter PCL, the PC high preload register PCLATH, and the master interrupt control register INTCON.)

The PCLATH register supplies high-order instruction address bits when the 8 bits supplied by a write to the PCL register, or the 11 bits supplied by a <code>GOTO</code> or <code>CALL</code> instruction, are not sufficient to address the available ROM space.

===PIC17===
The PIC17 series never became popular and has been superseded by the PIC18 architecture (however, see [[#PKK Milandr|clones]] below). The PIC17 series is not recommended for new designs, and availability may be limited to users.

Improvements over earlier cores are 16-bit wide opcodes (allowing many new instructions), and a 16-level deep call stack. PIC17 devices were produced in packages from 40 to 68 pins.

The PIC17 series introduced a number of important new features:<ref>{{cite web |url=http://ww1.microchip.com/downloads/en/DeviceDoc/30412c.pdf |title=PIC17C4x microcontroller data sheet |publisher=Microchip Technology |year=1996 |access-date=2016-08-16 |id=DS30412C}}</ref>

* a memory mapped accumulator
* read access to code memory (table reads)
* direct register-to-register moves (prior cores needed to move registers through the accumulator)
* an external program memory interface to expand the code space
* an 8-bit × 8-bit hardware multiplier
* a second indirect register pair
* auto-increment/auto-decrement addressing controlled by control bits in a status register (ALUSTA)

A significant limitation was that RAM space was limited to 256 bytes (26 bytes of special function registers, and 232 bytes of general-purpose RAM), with awkward bank-switching in the models that supported more.

===PIC18===
{{Further|topic=this family of microcontrollers|PIC instruction listings#PIC18 high end core devices (16 bit)}}
In 2000, Microchip introduced the PIC18 architecture. Unlike the PIC17 series, it has proven to be very popular, with a large number of device variants presently in manufacture. In contrast to earlier devices, which were more often than not programmed in [[assembly language]], [[C programming language|C]] has become the predominant development language.<ref>{{cite web|url=http://www.microchipc.com/sourcecode/|title=Microchip PIC micros and C - source and sample code|website=www.microchipc.com|access-date=7 April 2018}}</ref>

The PIC18 series inherits most of the features and instructions of the PIC17 series, while adding a number of important new features:

* call stack is 21 bits wide and much deeper (31 levels deep)
* the call stack may be read and written (TOSU:TOSH:TOSL registers)
* conditional branch instructions
* indexed addressing mode (PLUSW)
* the FSR registers are extended to 12 bits, allowing them to linearly address the entire data address space
* the addition of another FSR register (bringing the number up to 3)

The RAM space is 12&nbsp;bits, addressed using a 4-bit bank select register (BSR) and an 8-bit offset in each instruction. An additional "access" bit in each instruction selects between bank 0 (''a''=0) and the bank selected by the BSR (''a''=1).

A 1-level stack is also available for the STATUS, WREG and BSR registers. They are saved on every interrupt, and may be restored on return. If interrupts are disabled, they may also be used on subroutine call/return by setting the ''s'' bit (appending ", FAST" to the instruction).

The auto increment/decrement feature was improved by removing the control bits and adding four new indirect registers per FSR. Depending on which indirect file register is being accessed, it is possible to postdecrement, postincrement, or preincrement FSR; or form the effective address by adding W to FSR.

In more advanced PIC18 devices, an "extended mode" is available which makes the addressing even more favorable to compiled code:

* a new offset addressing mode; some addresses which were relative to the access bank are now interpreted relative to the FSR2 register
* the addition of several new instructions, notably for manipulating the FSR registers.

PIC18 devices are still developed (2021) and fitted with CIP (Core Independent Peripherals)

===PIC24 and dsPIC===
{{Further|topic=these families of microcontrollers|PIC instruction listings#PIC24 and dsPIC 16-bit microcontrollers}}
In 2001, Microchip introduced the dsPIC series of chips,<ref>{{Cite web |url=http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529 |title=MICROCHIP TECHNOLOGY DEBUTS WORLD'S HIGHEST PERFORMING 16-BIT MICROCONTROLLERS |publisher=Microchip |date=2001-10-01 |archive-url=https://web.archive.org/web/20040611032643/http://www.microchip.com/stellent/idcplg?IdcService=SS_GET_PAGE&nodeId=2018&mcparam=en013529 |archive-date=2004-06-11 |access-date=2022-12-14}}</ref> which entered mass production in late 2004. They are Microchip's first inherently 16-bit microcontrollers. PIC24 devices are designed as general purpose microcontrollers. dsPIC devices include [[digital signal processing]] capabilities in addition.

Although still similar to earlier PIC architectures, there are significant enhancements:<ref>{{cite web |title= PIC24H Family Overview |url=http://ww1.microchip.com/downloads/en/DeviceDoc/70166A.pdf |access-date=23 September 2007}}</ref>

* All registers are 16 bits wide
* [[Program counter]] is 22 bits (bits 22:1; bit 0 is always 0)
* Instructions are 24 bits wide
* Data address space expanded to 64&nbsp;[[Kibibyte|KiB]]
* First 2&nbsp;KiB is reserved for peripheral control registers
* Data bank switching is not required unless RAM exceeds 62&nbsp;KiB
* "f operand" direct addressing extended to 13 bits (8&nbsp;KiB)
* 16 W registers available for register-register operations.<br />(But operations on f operands always reference W0.)
* Instructions come in byte and (16-bit) word forms
* Stack is in RAM (with W15 as stack pointer); there is no hardware stack
* W14 is the [[frame pointer]]
* Data stored in ROM may be accessed directly ("Program Space Visibility")
* [[Vectored Interrupt|Vectored interrupt]]s for different interrupt sources

Some features are:

* (16×16)-bit single-cycle multiplication and other [[digital signal processing]] operations
* hardware [[multiply–accumulate]] (MAC)
* hardware divide assist (19 cycles for 32/16-bit divide)
* [[barrel shifter|barrel shifting]] - for both accumulators and general purpose registers
* bit reversal
* hardware support for loop indexing
* peripheral [[direct memory access]]

dsPICs can be programmed in [[C (programming language)|C]] using Microchip's XC16 compiler (formerly called C30), which is a variant of [[GNU Compiler Collection|GCC]].

Instruction ROM is 24 bits wide. Software can access ROM in 16-bit words, where even words hold the least significant 16 bits of each instruction, and odd words hold the most significant 8 bits. The high half of odd words reads as zero. The program counter is 23 bits wide, but the least significant bit is always 0, so there are 22 modifiable bits.

Instructions come in two main varieties, with most important operations (add, xor, shifts, etc.) allowing both forms:

* The first is like the classic PIC instructions, with an operation between a specified f register (i.e. the first 8K of RAM) and a single accumulator W0, with a destination select bit selecting which is updated with the result. (The W registers are memory-mapped. so the f operand may be any W register.)
* The second form is more conventional, allowing three operands, which may be any of 16 W registers. The destination and one of the sources also support addressing modes, allowing the operand to be in memory pointed to by a W register.

===PIC32M MIPS-based line===
Microchip's PIC32M products use the PIC trademark, but have a completely different architecture, and are described here only briefly.

====PIC32MX====
In November 2007, Microchip introduced the [https://ww1.microchip.com/downloads/en/DeviceDoc/61177a.pdf PIC32MX] family of 32-bit microcontrollers, based on the [[MIPS instruction set|MIPS32 M4K Core]].<ref>{{cite web |url=http://www.mips.com/products/processors/32-64-bit-cores/mips32-m4k/ |title=MIPS32® M4K® Core - MIPS Technologies -MIPS Everywhere - MIPS Technologies |access-date=2009-01-21 |url-status=dead |archive-url=https://web.archive.org/web/20090202094206/http://mips.com/products/processors/32%2D64%2Dbit%2Dcores/mips32%2Dm4k/ |archive-date=2009-02-02 }}</ref> The device can be programmed using the [https://archive.today/20130128153047/http://microchip.com/c32 Microchip MPLAB C Compiler for PIC32 MCUs], a variant of the GCC compiler. The first 18 models currently in production (PIC32MX3xx and PIC32MX4xx) are pin to pin compatible and share the same peripherals set with the PIC24FxxGA0xx family of (16-bit) devices, allowing the use of common libraries, software and hardware tools. Today, starting at 28 pin in small QFN packages up to high performance devices with Ethernet, CAN and USB OTG, full family range of mid-range 32-bit microcontrollers are available.

The PIC32 architecture brought a number of new features to Microchip portfolio, including:

* The highest execution speed 80&nbsp;MIPS (120+<ref>{{cite web |title=32-bit PIC MCUs |url=http://www.microchip.com/en_US/family/pic32/ |access-date=13 October 2010}}</ref> [[Dhrystone]] {{nowrap|MIPS @ 80 MHz}})
* The largest flash memory: 512&nbsp;kB
* One instruction per clock cycle execution
* The first cached processor
* Allows execution from RAM
* Full Speed Host/Dual Role and OTG USB capabilities
* Full [[JTAG]] and 2-wire programming and debugging
* Real-time trace

====PIC32MZ====
In November 2013, Microchip introduced the PIC32MZ series of microcontrollers, based on the [[MIPS instruction set|MIPS]] M14K core. The PIC32MZ series include:<ref>{{cite web|url=https://www.microchip.com/design-centers/32-bit|title=32-Bit MCUs - Microchip Technology|website=www.microchip.com|access-date=7 April 2018}}</ref><ref>{{cite web |url=http://www.microchip.com/pagehandler/en-us/press-release/microchips-pic32mz-32-bit-mcus.html |title=Microchip's PIC32MZ 32-bit MCUs Have Class-Leading Performance of 330 DMIPS and 3.28 CoreMarks™/MHz; 30% Better Code Density |publisher=Microchip |date=2013-11-18 |archive-url=https://web.archive.org/web/20131121032105/http://www.microchip.com/pagehandler/en-us/press-release/microchips-pic32mz-32-bit-mcus.html |archive-date=2013-11-21 |access-date=2022-12-14}}</ref>

* 252&nbsp;MHz core speed, 415 DMIPS
* Up to 2&nbsp;MB Flash and 512&nbsp;KB RAM
* New peripherals including high-speed USB, crypto engine and [[Serial Peripheral Interface#QPI/SQI|SQI]]

In 2015, Microchip released the PIC32MZ EF family, using the updated MIPS M5150 Warrior M-class processor.<ref>{{cite web|url=http://blog.imgtec.com/mips-processors/microchip-upgrades-pic32mz-ef-family-to-mips-m-class-m5150-mcu|title=Welcome to the Imagination Blog|website=imgtec.com|access-date=7 April 2018}}</ref><ref>{{Cite web|url=http://www.microchip.com/design-centers/32-bit/architecture/pic32mz-family|title = PIC32MZ EF &#124; Microchip Technology}}</ref>

In 2017, Microchip introduced the PIC32MZ DA Family, featuring an integrated graphics controller, graphics processor and 32MB of DDR2 DRAM.<ref>{{cite web|url=https://www.microchip.com/pressreleasepage/microchip-introduces-PIC32MZDA|archive-url=https://web.archive.org/web/20170720200010/https://www.microchip.com/pressreleasepage/microchip-introduces-PIC32MZDA|archive-date=2017-07-20|title=Microchip Introduces the Industry's First MCU with Integrated 2D GPU and Integrated DDR2 Memory for Groundbreaking Graphics Capabilities|access-date=2023-08-09}}</ref><ref>{{cite web |url=http://www.microchip.com/design-centers/32-bit/architecture/pic32mz-da-family |title=PIC32MZ DA Family |publisher=Microchip |archive-url=https://web.archive.org/web/20180402133356/http://www.microchip.com/design-centers/32-bit/architecture/pic32mz-da-family/ |archive-date=2018-04-02 |access-date=2022-12-14}}</ref>

====PIC32MM====
In June 2016, Microchip introduced the PIC32MM family, specialized for low-power and low-cost applications.<ref>{{cite web|url=https://www.microchip.com/en/pressreleasepage/microchip-launches-lowest-power-cost-effective-pic32-family|title=Microchip Launches Lowest Power, Cost-Effective PIC32 Family - Microchip Technology|website=www.microchip.com|access-date=7 April 2018}}</ref> The PIC32MM features core-independent peripherals, sleep modes down to 500 nA, and 4 x 4&nbsp;mm packages.<ref>{{cite web|url=https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mcus/pic32-32-bit-mcus/pic32mm|title=PIC32MM Family of eXtreme Low Power (XLP), Low Cost, 32-bit Microcontrollers|access-date=2023-08-09}}</ref> The PIC32MM microcontrollers use the [[MIPS Technologies]] M4K, a 32-bit [[MIPS architecture|MIPS32]] processor.
They are meant for very low power consumption and limited to 25&nbsp;MHz.
Their key advantage is to support the 16-bit instructions of MIPS, making program size much more compact (about 40%)

====PIC32MK====
Microchip introduced the PIC32MK family in 2017, specialized for motor control, industrial control, Industrial Internet of Things (IIoT) and multi-channel CAN applications.<ref>{{cite web |url=http://www.microchip.com/design-centers/32-bit/architecture/pic32mk-family |title=PIC32MK Family |publisher=Microchip |archive-url=https://web.archive.org/web/20180316231945/http://www.microchip.com/design-centers/32-bit/architecture/pic32mk-family |archive-date=2018-03-16 |access-date=2022-12-14}}</ref>

===PIC32C Arm-based line===
Microchip's PIC32C products also use the PIC trademark, but similarly have a completely different architecture. PIC32C products employ the Arm processor architecture, including various lines using Cortex-M0+, M4, M7, M23, and M33 cores. They are offered in addition to the Arm-based SAM series of MCUs which Microchip inherited from its acquisition of Atmel.<ref>{{cite web |url=https://www.microchip.com/en-us/products/microcontrollers-and-microprocessors/32-bit-mcus |title=32-bit PIC® and SAM Microcontrollers |publisher=Microchip |access-date=2024-08-22}}</ref>

=== PIC64 ===
Microchip's PIC64 products use the PIC trademark, but have a completely different architecture, and are described here only briefly.

In July 2024, Microchip introduced the PIC64 series of high-performance multi-core [[microprocessor]]s. The series will initially use the [[RISC-V]] instruction set, however Microchip is also planning versions with [[ARM Cortex-A]] cores.<ref>{{Cite press release |last=anisha |title=Microchip starts 64bit PIC64 family with RISC-V |publisher=RISC-V International |date=12 July 2024 |url=https://riscv.org/news/2024/07/microchip-starts-64bit-pic64-family-with-risc-v-2/ |access-date=2024-07-24 |language=en-US}}</ref> The PIC64 series will include the PIC64GX line, which focuses on intelligent edge applications, and the PIC64-HPSC line, which is [[Radiation hardening|radiation-hardened]] and focuses on spaceflight applications.<ref>{{Cite press release |title=Microchip Unveils 64-Bit Multi-Core PIC64 Portfolio |first=James |last=Lewis |date=9 July 2024 |url=https://www.hackster.io/news/microchip-unveils-64-bit-multi-core-pic64-portfolio-672ff16bd042 |access-date=2024-07-24 |publisher=Microchip |via=Hackster.io |language=en}}</ref><ref>{{cite press release |title=Moog Unveils New, Radiation-Hardened Space Computer to Support the Next Generation of High-Speed Computing On-Orbit |publisher=[[Moog Inc.]] |date=13 August 2024 |url=https://spacenews.com/moog-unveils-new-radiation-hardened-space-computer-to-support-the-next-generation-of-high-speed-computing-on-orbit/ |via=[[SpaceNews]]}}</ref>