Editing Peripheral Component Interconnect (section)

==Conventional hardware specifications==
[[File:PCI Keying.svg|thumb|upright=1.5|Diagram showing the different key positions for 32-bit and 64-bit PCI cards]]

These specifications represent the most common version of PCI used in normal PCs:
* {{nowrap|33.33 MHz}} [[clock signal|clock]] with [[Synchronous circuit|synchronous]] transfers
* Peak transfer rate of 133&nbsp;[[Megabyte|MB]]/s (133 [[megabyte]]s per second) for 32-bit bus width (33.33&nbsp;MHz × 32&nbsp;bits ÷ 8&nbsp;bits/byte = 133&nbsp;MB/s)
* [[32-bit computing|32-bit]] bus width
* 32- or 64-bit memory address space (4&nbsp;[[gibibyte|GiB]] or 16&nbsp;[[exbibyte|EiB]])
* 32-bit I/O port space
* 256-[[byte]] (per device) configuration space
* 5-volt signaling
* [[Reflected-wave switching]]

The PCI specification also provides options for 3.3&nbsp;V signaling, [[64-bit computing|64-bit]] bus width, and 66&nbsp;MHz clocking, but these are not commonly encountered outside of PCI-X support on server motherboards.

The PCI bus arbiter performs bus arbitration among multiple masters on the PCI bus. Any number of bus masters can reside on the PCI bus, as well as requests for the bus. One pair of request and grant signals is dedicated to each bus master.

===Card voltage and keying===
[[File:Intelpromtserverpcixadapter1000mta342.jpg|thumb|A PCI-X [[Gigabit Ethernet]] expansion card with both 5&nbsp;V and 3.3&nbsp;V support notches, side B toward the camera]]

Typical PCI cards have either one or two key notches, depending on their signaling voltage. Cards requiring 3.3&nbsp;volts have a notch 56.21&nbsp;mm from the card backplate; those requiring 5&nbsp;volts have a notch 104.41&nbsp;mm from the backplate. This allows cards to be fitted only into slots with a voltage they support. "Universal cards" accepting either voltage have both key notches.

===Connector pinout===
The PCI connector is defined as having 62 contacts on each side of the [[edge connector]], but two or four of them are replaced by key notches, so a card has 60 or 58 contacts on each side.  Side A refers to the 'solder side' and side B refers to the 'component side': if the card is held with the connector pointing down, a view of side A will have the backplate on the right, whereas a view of side B will have the backplate on the left. The pinout of B and A sides are as follows, looking down into the motherboard connector (pins A1 and B1 are closest to backplate).<ref name=pci30>PCI Local Bus Specification, revision 3.0</ref><ref name=pci23>{{cite book|title=PCI Local Bus Specification Revision 2.3 |date=March 29, 2002 |author=<!--Staff writer(s); no by-line.-->|publisher=[[PCI-SIG|PCI Special Interest Group]]|location=[[Portland, Oregon]]}}</ref><ref>{{cite web| url = http://www.allpinouts.org/index.php/PCI| title = PCI Connector Pinout}}</ref><!-- WARNING: POST NO LINKS TO ANY PIRATED PCI SPECS, NOR DESCRIBE WHERE TO FIND THEM. See DMCA take-down notice at [[wmf:File:DMCA PCI.pdf]] -->

{|class=wikitable
|+ 32-bit PCI connector pinout
! Pin !!colspan="2"| Side B !!colspan="2"| Side A !! Comments
|-
! 1
|align=center colspan="2" style="background:silver"| −12&nbsp;V ||align=center colspan="2" style="background:#66f"| TRST# ||rowspan=4| [[JTAG]] port pins (optional)
|-
! 2
|align=center colspan="2" style="background:#66f"| TCK  ||align=center colspan="2" style="background:silver"| +12&nbsp;V
|-
! 3
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#66f"| TMS
|-
! 4
|align=center colspan="2" style="background:#f69"| TDO ||align=center colspan="2" style="background:#66f"| TDI
|-
! 5
|align=center colspan="2" style="background:silver"| +5&nbsp;V ||align=center colspan="2" style="background:silver"| +5&nbsp;V ||
|-
! 6
|align=center colspan="2" style="background:silver"| +5&nbsp;V ||align=center colspan="2" style="background:#fc6"| INTA# ||rowspan=3|Interrupt pins (open-drain)
|-
! 7
|align=center colspan="2" style="background:#fc6"| INTB# ||align=center colspan="2" style="background:#fc6"| INTC#
|-
! 8
|align=center colspan="2" style="background:#fc6"| INTD# ||align=center colspan="2" style="background:silver"| +5&nbsp;V
|-
! 9
|align=center colspan="2" style="background:#f69"| PRSNT1# ||align=center colspan="2" style="background:#ff9"| Reserved || Pulled low to indicate 7.5 or 25 W power required
|-
! 10
|align=center colspan="2" style="background:#ff9"| Reserved ||align=center colspan="2" style="background:silver"| IOPWR || +5&nbsp;V or +3.3&nbsp;V
|-
! 11
|align=center colspan="2" style="background:#f69"| PRSNT2# ||align=center colspan="2" style="background:#ff9"| Reserved || Pulled low to indicate 7.5 or 15 W power required
|-
! 12
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#999"| Ground ||rowspan=2| Key notch for 3.3&nbsp;V-capable cards
|-
! 13
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#999"| Ground
|-
! 14
|align=center colspan="2" style="background:#ff9"| Reserved ||align=center colspan="2" style="background:silver"| 3.3&nbsp;V&nbsp;aux || [[Standby power]] (optional)
|-
! 15
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#66f"| RST# || Bus reset
|-
! 16
|align=center colspan="2" style="background:#66f"| CLK ||align=center colspan="2" style="background:silver"| IOPWR || 33/66&nbsp;MHz clock
|-
! 17
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#66f"| GNT# || Bus grant from motherboard to card
|-
! 18
|align=center colspan="2" style="background:#f69"| REQ# ||align=center colspan="2" style="background:#999"| Ground || Bus request from card to motherboard
|-
! 19
|align=center colspan="2" style="background:silver"| IOPWR ||align=center colspan="2" style="background:#fc6"| PME# || Power management event (optional) 3.3&nbsp;V, open drain, active low.<ref name=pcipwr12>PCI Power
Management Interface Specification v1.2</ref>
|-
! 20
|align=center colspan="2" style="background:#9f9"| AD[31] ||align=center colspan="2" style="background:#9f9"| AD[30] ||rowspan=14| Address/data bus (upper half)
|-
! 21
|align=center colspan="2" style="background:#9f9"| AD[29] ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V
|-
! 22
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#9f9"| AD[28]
|-
! 23
|align=center colspan="2" style="background:#9f9"| AD[27] ||align=center colspan="2" style="background:#9f9"| AD[26]
|-
! 24
|align=center colspan="2" style="background:#9f9"| AD[25] ||align=center colspan="2" style="background:#999"| Ground
|-
! 25
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center colspan="2" style="background:#9f9"| AD[24]
|-
! 26
|align=center colspan="2" style="background:#f9f"| C/BE[3]# ||align=center colspan="2" style="background:#66f"| IDSEL
|-
! 27
|align=center colspan="2" style="background:#9f9"| AD[23] ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V
|-
! 28
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#9f9"| AD[22]
|-
! 29
|align=center colspan="2" style="background:#9f9"| AD[21] ||align=center colspan="2" style="background:#9f9"| AD[20]
|-
! 30
|align=center colspan="2" style="background:#9f9"| AD[19] ||align=center colspan="2" style="background:#999"| Ground
|-
! 31
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center colspan="2" style="background:#9f9"| AD[18]
|-
! 32
|align=center colspan="2" style="background:#9f9"| AD[17] ||align=center colspan="2" style="background:#9f9"| AD[16]
|-
! 33
|align=center colspan="2" style="background:#f9f"| C/BE[2]# ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V
|-
! 34
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#f9f"| FRAME# || Bus transfer in progress
|-
! 35
|align=center colspan="2" style="background:#f9f"| IRDY# ||align=center colspan="2" style="background:#999"| Ground || Initiator ready
|-
! 36
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center colspan="2" style="background:#99f"| TRDY# || Target ready
|-
! 37
|align=center colspan="2" style="background:#99f"| DEVSEL# ||align=center colspan="2" style="background:#999"| Ground || Target selected
|-
! 38
|align=center style="background:#fc6"| PCIXCAP ||align=center style="background:#999"| Ground ||align=center colspan="2" style="background:#99f"| STOP# || [[PCI-X]] capable; Target requests halt
|-
! 39
|align=center colspan="2" style="background:#f9f"| LOCK# ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V || Locked transaction
|-
! 40
|align=center colspan="2" style="background:#f69"| PERR# ||align=center style="background:#fc6"| SMBCLK ||align=center style="background:#f9f"| ''SDONE'' || Parity error; [[SMBus]] clock or ''Snoop done (obsolete)''
|-
! 41
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center style="background:#fc6"| SMBDAT ||align=center style="background:#f9f"|''SBO#'' || SMBus data or ''Snoop backoff (obsolete)''
|-
! 42
|align=center colspan="2" style="background:#fc6"| SERR# ||align=center colspan="2" style="background:#999"| Ground || System error
|-
! 43
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center colspan="2" style="background:#9f9"| PAR || Even parity over AD[31:00] and C/BE[3:0]#
|-
! 44
|align=center colspan="2" style="background:#f9f"| C/BE[1]# ||align=center colspan="2" style="background:#9f9"| AD[15] ||rowspan=6| Address/data bus (higher half)
|-
! 45
|align=center colspan="2" style="background:#9f9"| AD[14] ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V
|-
! 46
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#9f9"| AD[13]
|-
! 47
|align=center colspan="2" style="background:#9f9"| AD[12] ||align=center colspan="2" style="background:#9f9"| AD[11]
|-
! 48
|align=center colspan="2" style="background:#9f9"| AD[10] ||align=center colspan="2" style="background:#999"| Ground
|-
! 49
|align=center style="background:#fc6"| M66EN ||align=center style="background:#999"| Ground ||align=center colspan="2" style="background:#9f9"| AD[09]
|-
! 50
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#999"| Ground ||rowspan=2| Key notch for 5&nbsp;V-capable cards
|-
! 51
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#999"| Ground
|-
! 52
|align=center colspan="2" style="background:#9f9"| AD[08] ||align=center colspan="2" style="background:#f9f"| C/BE[0]# ||rowspan=7| Address/data bus (lower half)
|-
! 53
|align=center colspan="2" style="background:#9f9"| AD[07] ||align=center colspan="2" style="background:silver"| +3.3&nbsp;V
|-
! 54
|align=center colspan="2" style="background:silver"| +3.3&nbsp;V ||align=center colspan="2" style="background:#9f9"| AD[06]
|-
! 55
|align=center colspan="2" style="background:#9f9"| AD[05] ||align=center colspan="2" style="background:#9f9"| AD[04]
|-
! 56
|align=center colspan="2" style="background:#9f9"| AD[03] ||align=center colspan="2" style="background:#999"| Ground
|-
! 57
|align=center colspan="2" style="background:#999"| Ground ||align=center colspan="2" style="background:#9f9"| AD[02]
|-
! 58
|align=center colspan="2" style="background:#9f9"| AD[01] ||align=center colspan="2" style="background:#9f9"| AD[00]
|-
! 59
|align=center colspan="2" style="background:silver"| IOPWR ||align=center colspan="2" style="background:silver"| IOPWR ||
|-
! 60
|align=center colspan="2" style="background:#99f"| ACK64# ||align=center colspan="2" style="background:#f9f"| REQ64# || For 64-bit extension; no connect for 32-bit devices.
|-
! 61
|align=center colspan="2" style="background:silver"| +5&nbsp;V ||align=center colspan="2" style="background:silver"| +5&nbsp;V ||rowspan=2|
|-
! 62
|align=center colspan="2" style="background:silver"| +5&nbsp;V ||align=center colspan="2" style="background:silver"| +5&nbsp;V
|}

64-bit PCI extends this by an additional 32 contacts on each side which provide AD[63:32], C/BE[7:4]#, the PAR64 parity signal, and a number of power and ground pins.

{|class=wikitable
|+ Legend
!style="background:#999"| Ground pin
| Zero volt reference
|-
!style="background:silver"| Power pin
| Supplies power to the PCI card
|-
!style="background:#f69"| Output pin
| Driven by the PCI card, received by the motherboard
|-
!style="background:#f9f"| Initiator output
| Driven by the master/initiator, received by the target
|-
!style="background:#9f9"|I/O signal
| May be driven by initiator or target, depending on operation
|-
!style="background:#99f"| Target output
| Driven by the target, received by the initiator/master
|-
!style="background:#66f"| Input
| Driven by the motherboard, received by the PCI card
|-
!style="background:#fc6"| [[Open drain]]
| May be pulled low and/or sensed by multiple cards
|-
!style="background:#ff9"| Reserved
| Not presently used, do not connect
|}

Most lines are connected to each slot in parallel.  The exceptions are:
* Each slot has its own REQ# output to, and GNT# input from the motherboard arbiter.
* Each slot has its own IDSEL line, usually connected to a specific AD line.
* TDO is daisy-chained to the following slot's TDI. Cards without [[JTAG]] support must connect TDI to TDO so as not to break the chain.
* PRSNT1# and PRSNT2# for each slot have their own pull-up resistors on the motherboard. The motherboard may (but does not have to) sense these pins to determine the presence of PCI cards and their power requirements.
* REQ64# and ACK64# are individually pulled up on 32-bit only slots.
* The interrupt pins INTA# through INTD# are connected to all slots in different orders. (INTA# on one slot is INTB# on the next and INTC# on the one after that.)

Notes:
* IOPWR is +3.3&nbsp;V or +5&nbsp;V, depending on the backplane. The slots also have a ridge in one of two places which prevents insertion of cards that do not have the corresponding key notch, indicating support for that voltage standard. Universal cards have both key notches and use IOPWR to determine their I/O signal levels.
* The PCI SIG strongly encourages 3.3&nbsp;V PCI signaling,<ref name=pci30/> requiring support for it since standard revision 2.3,<ref name=pci23/> but most PC motherboards use the 5&nbsp;V variant.  Thus, while many currently available PCI cards support both, and have two key notches to indicate that, there are still a large number of 5&nbsp;V-only cards on the market.
* The M66EN pin is an additional ground on 5&nbsp;V PCI buses found in most PC motherboards. Cards and motherboards that do not support 66&nbsp;MHz operation also ground this pin. If all participants support 66&nbsp;MHz operation, a pull-up resistor on the motherboard raises this signal high and 66&nbsp;MHz operation is enabled. The pin is still connected to ground via [[coupling capacitor]]s on each card to preserve its [[Alternating current|AC]] shielding function.
* The PCIXCAP pin is an additional ground on PCI buses and cards. If all cards and the motherboard support the [[PCI-X]] protocol, a pull-up resistor on the motherboard raises this signal high and PCI-X operation is enabled.  The pin is still connected to ground via coupling capacitors on each card to preserve its AC shielding function.<!--It's actually more complicated than that, but this isn't the place to go into details.-->
* At least one of PRSNT1# and PRSNT2# must be grounded by the card. The combination chosen indicates the total power requirements of the card (25&nbsp;W, 15&nbsp;W, or 7.5&nbsp;W).
* SBO# and SDONE are signals from a cache controller to the current target. They are not initiator outputs, but are colored that way because they are target inputs.
* PME# ({{nowrap|19 A}}){{snd}} Power management event (optional) which is supported in PCI {{nowrap|version 2.2}} and higher. It is a {{nowrap|3.3 V}}, [[Open collector|open drain]], active low signal.<ref name=pcipwr12 />  PCI cards may use this signal to send and receive PME via the PCI socket directly, which eliminates the need for a special [[Wake-on-LAN#Hardware implementations|Wake-on-LAN cable]].<ref>{{cite web |url = http://xlife.zuavra.net/index.php/60/ |title = archive.org/zuavra.net - Using Wake-On-LAN WOL/PME to power up your computer remotely |archive-url=https://web.archive.org/web/20070308143030/http://xlife.zuavra.net/index.php/60/ |archive-date=8 March 2007 |url-status=dead}}</ref>

===Mixing of 32-bit and 64-bit PCI cards in different width slots===
[[File:PCI-X in a 32-bit slot.jpg|thumb|A semi-inserted PCI-X card in a 32-bit PCI slot, illustrating the need for the rightmost notch and the extra room on the motherboard to remain backward compatible]]
[[File:64bit PCI SCSI card in a 32bit PCI slot.jpg|thumb|64-bit SCSI card working in a 32-bit PCI slot]]
Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus clock rate will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3, 66-MHz peripheral is installed into a PCI-X bus capable of 133&nbsp;MHz, the entire bus backplane will be limited to 66&nbsp;MHz. To get around this limitation, many motherboards have two or more PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.

Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of performance.<ref>{{cite web
 |url          = http://docs.znyx.com/products/hardware/zx370.htm
 |title        = ZX370 Series
 |access-date   = July 13, 2012
 |author       = ZNYX Networks
 |date         = June 16, 2009
 |quote        = The ZX370 Series is a true 64-bit adapter, widening the network pipeline to achieve higher throughput while offering backward compatibility with standard 32-bit PCI slots.
 |archive-url  = https://web.archive.org/web/20110502042329/http://docs.znyx.com/products/hardware/zx370.htm
 |archive-date = May 2, 2011
 |url-status   = dead
}}</ref><ref>{{cite web
| url          = http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf
| title        = ZX370 Series Multi-Channel PCI Fast Ethernet Adapter
| access-date   = July 13, 2012
| author       = ZNYX Networks
| quote        = Backward compatible with 32 bit, 33&nbsp;MHz PCI slots
| archive-url  = https://web.archive.org/web/20130720174917/http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf
| archive-date = July 20, 2013
| url-status   = dead
}}</ref> An example of this is the Adaptec 29160 64-bit [[SCSI]] interface card.<ref>{{cite web
| url         = http://www.adaptec.com/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm?nc=/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm
| title       = Adaptec SCSI Card 29160 Ultra160 SCSI Controller User's Reference
| access-date  = July 13, 2012
| author      = Adaptec
|date=January 2000
| format      = pdf
| page        = 1
| quote       = Although the Adaptec SCSI Card 29160 is a 64-bit PCI card, it also works in a 32-bit PCI slot. When installed in a 32-bit PCI slot, the card automatically runs in the slower 32-bit mode.
}}</ref> However, some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.<ref>{{cite web
 |url=http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164 
 |title=LaCie support: Identify a variety of PCI slots 
 |access-date=July 13, 2012 
 |author=LaCie 
 |url-status=dead 
 |archive-url=https://web.archive.org/web/20120404080344/http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164 
 |archive-date=April 4, 2012 
}}</ref>{{Unreliable source?|date=July 2012}}

Installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging. This requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.{{clear}}