Editing Phase-change memory (section)

==2000 and later==
In August 2004, Nanochip licensed PRAM technology for use in [[Microelectromechanical systems|MEMS]] (micro-electric-mechanical-systems) probe storage devices. These devices are not [[Solid-state drive|solid state]]. Instead, a very small platter coated in [[chalcogenide]] is dragged beneath thousands or even millions of electrical probes that can read and write the chalcogenide. [[Hewlett-Packard]]'s micro-mover technology can accurately position the platter to 3[[Nanometre|&nbsp;nm]] so densities of more than 1[[Terabit|&nbsp;Tbit]] (125[[Gigabyte|&nbsp;GB]]) per square inch will be possible if the technology can be perfected. The basic idea is to reduce the amount of wiring needed on-chip; instead of wiring every cell, the cells are placed closer together and read by current passing through the MEMS probes, acting like wires. This approach resembles [[IBM]]'s [[IBM Millipede|Millipede]] technology.

===Samsung 46.7 nm cell===
In September 2006, [[Samsung]] announced a prototype 512[[Megabit|&nbsp;Mb]] (64[[Megabyte|&nbsp;MB]]) device using [[diode]] switches.<ref name=samsung>[http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=766.0 SAMSUNG Introduces the Next Generation of Nonvolatile Memory—PRAM]</ref> The announcement was something of a surprise, and it was especially notable for its fairly high [[Density (computer storage)|memory density]]. The prototype featured a cell size of only 46.7&nbsp;nm, smaller than commercial [[Flash memory|flash]] devices available at the time. Although flash devices of higher ''capacity'' were available (64[[Gigabit|&nbsp;Gb]], or 8[[Gigabyte|&nbsp;GB]], was just coming to market), other technologies competing to replace flash in general offered lower densities (larger cell sizes). The only production [[Magnetoresistive RAM|MRAM]] and [[FeRAM]] devices are only 4&nbsp;Mb, for example. The high density of Samsung's prototype PRAM device suggested it could be a viable flash competitor, and not limited to niche roles as other devices have been. PRAM appeared to be particularly attractive as a potential [[NOR flash replacement|replacement for NOR flash]], where device capacities typically lag behind those of [[NAND flash memory|NAND]] flash devices. State-of-the-art capacities on NAND passed 512&nbsp;Mb some time ago. [[NOR flash]] offers similar densities to Samsung's PRAM prototype and already offers bit addressability (unlike NAND where memory is accessed in banks of many bytes at a time).

===Intel's PRAM device===
Samsung's announcement was followed by one from [[Intel]] and [[STMicroelectronics]], who demonstrated their own PRAM devices at the 2006 [[Intel Developer Forum]] in October.<ref>{{Cite web|url=http://www.eweek.com/article2/0,1895,2021822,00.asp|archive-url=https://archive.today/20120629111057/http://www.eweek.com/article2/0,1895,2021822,00.asp|url-status=dead|archive-date=June 29, 2012|title=Intel Previews Potential Replacement for Flash}}</ref> They showed a 128&nbsp;Mb part that began manufacture at STMicroelectronics's research lab in Agrate, Italy. Intel stated that the devices were strictly [[Proof of concept|proof-of-concept]].

===BAE device===
PRAM is also a promising technology in the military and aerospace industries where radiation effects make the use of standard [[Non-volatile memory|non-volatile memories]] such as flash impractical. PRAM devices have been introduced by [[BAE Systems]], referred to as C-RAM, claiming excellent radiation tolerance ([[rad-hard]]) and [[latchup]] immunity. In addition, BAE claims a write cycle endurance of 10<sup>8</sup>, which will allow it to be a contender for replacing [[Programmable read-only memory|PROM]]s and [[EEPROM]]s in space systems.

===Multi-level cell===
In February 2008, Intel and STMicroelectronics revealed the first multilevel ([[Multi-level Cell|MLC]]) PRAM array prototype. The prototype stored two logical bits in each physical cell, in effect 256&nbsp;Mb of memory stored in a 128&nbsp;Mb physical array. This means that instead of the normal two states—fully [[Amorphous solid|amorphous]] and fully [[crystal]]line—an additional two distinct intermediate states represent different degrees of partial crystallization, allowing for twice as many bits to be stored in the same physical area.<ref name=review/> In June 2011,<ref name="engadget article">{{cite web|title=IBM develops 'instantaneous' memory, 100x faster than flash| publisher=engadget|date=2011-06-30|url=https://www.engadget.com/2011/06/30/embargo-ibm-develops-instantaneous-memory-100x-faster-than-fl/|access-date=2011-06-30}}</ref> IBM announced that they had created stable, reliable, multi-bit phase-change memory with high performance and stability. [[SK Hynix]] had a joint developmental agreement and a technology license agreement with IBM for the development of multi-level PRAM technology.<ref>{{Cite web|last=|title=SK hynix and IBM Sign Joint Development for PCRAM|url=https://news.skhynix.com/sk-hynix-and-ibm-sign-joint-development-for-pcram/|access-date=2022-02-05|website=SK hynix Newsroom|language=en-US}}</ref>

===Intel's 90 nm device===
Also in February 2008, Intel and STMicroelectronics shipped prototype samples of their first PRAM product to customers. The 90&nbsp;nm, 128&nbsp;Mb (16&nbsp;MB) product was called Alverstone.<ref name="numonyx_sample">{{cite web|title=Intel, STMicroelectronics Deliver Industry's First Phase Change Memory Prototypes|publisher=Numonyx|date=2008-02-06|url=http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/IntelSTDeliverFirstPCMPrototypes.aspx|access-date=2008-08-15 |archive-url = https://web.archive.org/web/20080609215913/http://www.numonyx.com/en-US/About/PressRoom/Releases/Pages/IntelSTDeliverFirstPCMPrototypes.aspx <!-- Bot retrieved archive --> |archive-date = 2008-06-09}}</ref>

In June 2009, Samsung and [[Numonyx|Numonyx B.V.]] announced a collaborative effort in the development of PRAM market-tailored hardware products.<ref name="Samsung Electronics and Numonyx Join Forces on Phase Change Memory">{{cite web|title=Samsung Electronics and Numonyx Join Forces on Phase Change Memory| publisher=Samsung|date=2009-06-23|url=http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1023;articleID=1023}}</ref>

In April 2010,<ref name="eetimes article">{{cite web|title=Samsung to ship MCP with phase-change| publisher=EE Times|date=2010-04-28|url=http://www.eetimes.com/showArticle.jhtml;jsessionid=AZ0IF3RVEBPQVQE1GHPSKHWATMY32JVN?articleID=224700051|access-date=2010-05-03}}</ref> Numonyx announced the Omneo line of 128-Mbit NOR-compatible phase-change memories. Samsung announced shipment of 512&nbsp;Mb phase-change RAM (PRAM) in a multi-chip package (MCP) for use in mobile handsets by Fall 2010.

===ST 28 nm, 16&nbsp;MB array===
In December 2018 STMicroelectronics presented design and performance data for a 16&nbsp;MB ePCM array for a 28&nbsp;nm fully depleted [[silicon on insulator]] automotive control unit.<ref>{{Cite web |title=Phase-Change Memory (PCM) - Technology, Advantages & Applications - STMicroelectronics |url=https://www.st.com/content/st_com/en/about/innovation---technology/PCM.html |access-date=2022-07-08 |website=www.st.com |language=en}}</ref>

===In-memory computing===
More recently, there is significant interest in the application of PCM for in-memory computing.<ref>{{Cite journal|last1=Burr|first1=Geoffrey W.|last2=Shelby|first2=Robert M.|last3=Sidler|first3=Severin|last4=di Nolfo|first4=Carmelo|last5=Jang|first5=Junwoo|last6=Boybat|first6=Irem|last7=Shenoy|first7=Rohit S.|last8=Narayanan|first8=Pritish|last9=Virwani|first9=Kumar|last10=Giacometti|first10=Emanuele U.|last11=Kurdi|first11=Bulent N.|date=November 2015|title=Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element|url=https://ieeexplore.ieee.org/document/7151827|journal=IEEE Transactions on Electron Devices|volume=62|issue=11|pages=3498–3507|doi=10.1109/TED.2015.2439635|bibcode=2015ITED...62.3498B |s2cid=5243635 |issn=0018-9383|url-access=subscription}}</ref> The essential idea is to perform computational tasks such as [[Matrix multiplication algorithm|matrix-vector-multiply operations]] in the memory array itself by exploiting PCM's analog storage capability and [[Kirchhoff's circuit laws]]. PCM-based in-memory computing could be interesting for applications such as [[deep learning]] [[Statistical inference|inference]] which do not require very high computing precision.<ref>{{Cite journal|last1=Sebastian|first1=Abu|last2=Le Gallo|first2=Manuel|last3=Khaddam-Aljameh|first3=Riduan|last4=Eleftheriou|first4=Evangelos|date=July 2020|title=Memory devices and applications for in-memory computing|url=https://www.nature.com/articles/s41565-020-0655-z|journal=Nature Nanotechnology|language=en|volume=15|issue=7|pages=529–544|doi=10.1038/s41565-020-0655-z|pmid=32231270 |bibcode=2020NatNa..15..529S |s2cid=214704544 |issn=1748-3395|url-access=subscription}}</ref> In 2021, IBM published a full-fledged in-memory computing core based on multi-level PCM integrated in 14&nbsp;nm [[CMOS]] technology node.<ref>{{Cite journal|last1=Khaddam-Aljameh|first1=Riduan|last2=Stanisavljevic|first2=Milos|last3=Mas|first3=Jordi Fornt|last4=Karunaratne|first4=Geethan|last5=Brändli|first5=Matthias|last6=Liu|first6=Feng|last7=Singh|first7=Abhairaj|last8=Müller|first8=Silvia M.|last9=Egger|first9=Urs|last10=Petropoulos|first10=Anastasios|last11=Antonakopoulos|first11=Theodore|date=2022|title=HERMES-Core–A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs|journal=IEEE Journal of Solid-State Circuits|volume=57 |issue=4 |pages=1027–1038|doi=10.1109/JSSC.2022.3140414|bibcode=2022IJSSC..57.1027K |s2cid=246417395 |issn=1558-173X|doi-access=free}}</ref>