Editing Physical Address Extension (section)

=== 32-bit paging, 4 KiB pages, without PAE ===
[[File:X86 Paging 4K.svg|400px|thumb|right|No PAE, 4&nbsp;KB pages]]
In [[protected mode]] with paging enabled (bit&nbsp;31, <code>PG</code>, of control register <code>CR0</code> is set), but without PAE, [[x86]] processors use a two-level page translation scheme. [[Control register]] <code>CR3</code> holds the page-aligned physical address of a single 4&nbsp;KB long ''page directory''. This is divided into 1024 four-byte page directory entries that in turn, if valid, hold the page-aligned physical addresses of [[page table]]s, each 4&nbsp;KB in size. These similarly consist of 1024 four-byte page table entries which, if valid, hold the page-aligned physical addresses of 4&nbsp;KB long [[page (computing)|pages]] of physical memory (RAM).

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