Editing Programmable Array Logic (section)

===Programmable logic plane===
The programmable logic plane is a [[programmable read-only memory]] (PROM) array that allows the signals present on the device pins, or the logical complements of those signals, to be routed to output logic macrocells.

PAL devices have arrays of transistor cells arranged in a "fixed-OR, programmable-AND" plane used to implement "[[disjunctive normal form|sum-of-products]]" binary logic equations for each of the outputs in terms of the inputs and either synchronous or asynchronous feedback from the outputs.