Editing SIMM (section)

==Proprietary SIMMs==

===GVP 64-pin===
Several CPU cards from [[Great Valley Products]] for the [[Commodore International|Commodore]] [[Amiga]] used special 64-pin SIMMs (32 bits wide, 1, 4 or 16&nbsp;MB, 60&nbsp;ns).

===Apple 64-pin===
[[DPRAM|Dual-ported]] 64-pin SIMMs were used in [[Apple Inc.|Apple]] [[Macintosh IIfx]] computers to allow overlapping read/write cycles (1, 4, 8, 16&nbsp;MB, 80&nbsp;ns).<ref>[http://www.lowendmac.com/ii/macintosh-iifx.html Macintosh IIfx].</ref><ref>{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | page = 230}}</ref>

{|class="wikitable"
|+ 5V 64-pin Mac IIfx SIMM<ref>{{cite book | last = Apple Computer, Inc. | author-link = Apple Computer | title = Guide to the Macintosh Family Hardware | publisher = Addison-Wesley, Inc | year = 1990 | edition = 2nd | pages = 214–222}}</ref>
!Pin #!!Name!!Signal description
|rowspan=33|
!Pin #!!Name!!Signal description
|-
|1||GND||Ground
|33||Q4||Data output bus, bit 4
|-
|2||NC||Not connected
|34||/W4||Write-enable input for RAM IC 4
|-
|3||+5V||+5&nbsp;volts
|35||A8||Address bus, bit 8
|-
|4||+5V||+5&nbsp;volts
|36||NC||Not connected
|-
|5||/CAS||Column address strobe
|37||A9||Address bus, bit 9
|-
|6||D0||Data input bus, bit 0
|38||A10||Address bus, bit 10
|-
|7||Q0||Data output bus, bit 0
|39||A11||Address bus, bit 11
|-
|8||/W0||Write-enable input for RAM IC 0
|40||D5||Data input bus, bit 5
|-
|9||A0||Address bus, bit 0
|41||Q5||Data output bus, bit 5
|-
|10||NC||Not connected
|42||/W5||Write-enable input for RAM IC 5
|-
|11||A1||Address bus, bit 1
|43||NC||Not connected
|-
|12||D1||Data input bus, bit 1
|44||NC||Not connected
|-
|13||Q1||Data output bus, bit 1
|45||GND||Ground
|-
|14||/W1||Write-enable input for RAM IC 1
|46||D6||Data input bus, bit 6
|-
|15||A2||Address bus, bit 2
|47||Q6||Data output bus, bit 6
|-
|16||NC||Not connected
|48||/W6||Write-enable input for RAM IC 6
|-
|17||A3||Address bus, bit 3
|49||NC||Not connected
|-
|18||GND||Ground
|50||D7||Data input bus, bit 7
|-
|19||GND||Ground
|51||Q7||Data output bus, bit 7
|-
|20||D2||Data input bus, bit 2
|52||/W7||Write-enable input for RAM IC 7
|-
|21||Q2||Data output bus, bit 2
|53||/QB||Reserved (parity)
|-
|22||/W2||Write-enable input for RAM IC 2
|54||NC||Not connected
|-
|23||A4||Address bus, bit 4
|55||/RAS||Row address strobe
|-
|24||NC||Not connected
|56||NC||Not connected
|-
|25||A5||Address bus, bit 5
|57||NC||Not connected
|-
|26||D3||Data input bus, bit 3
|58||Q||Parity-check output
|-
|27||Q3||Data output bus, bit 3
|59||/WWP||Write wrong parity
|-
|28||/W3||Write-enable input for RAM IC 3
|60||PDCI||Parity daisy-chain input
|-
|29||A6||Address bus, bit 6
|61||+5V||+5&nbsp;volts
|-
|30||NC||Not connected
|62||+5V||+5&nbsp;volts
|-
|31||A7||Address bus, bit 7
|63||PDCO||Parity daisy-chain output
|-
|32||D4||Data input bus, bit 4
|64||GND||Ground
|}

===HP LaserJet===
72-pin SIMMs with [[HP LaserJet#Upgrading memory of older models|non-standard]] [[Serial presence detect|presence detect]] (PD) connections.