Editing Translation lookaside buffer (section)

==TLB-miss handling==
Three schemes for handling TLB misses are found in modern architectures:
* With hardware TLB management, the CPU automatically walks the [[page table]]s (using the [[Control register#CR3|CR3]] register on [[x86]], for instance) to see whether there is a valid page-table entry for the specified virtual address.  If an entry exists, it is brought into the TLB, and the TLB access is retried: this time the access will hit, and the program can proceed normally.  If the CPU finds no valid entry for the virtual address in the page tables, it raises a [[page fault]] [[exception handling|exception]], which the [[operating system]] must handle.  Handling page faults usually involves bringing the requested data into physical memory, setting up a page table entry to map the faulting virtual address to the correct physical address, and resuming the program.  With a hardware-managed TLB, the format of the TLB entries is not visible to software and can change from CPU to CPU without causing loss of compatibility for the operating system.
* With software-managed TLBs, a TLB miss generates a ''TLB miss'' exception, and operating system code is responsible for walking the page tables and finding the appropriate page table entry.  The operating system then loads the information from that page table entry into the TLB and restarts the program from the instruction that caused the TLB miss.  As with hardware TLB management, if the OS finds no valid translation in the page tables, a page fault has occurred, and the OS must handle it accordingly.  [[Instruction set]]s of CPUs that have software-managed TLBs have instructions that allow loading entries into any slot in the TLB. The format of the TLB entry is defined as a part of the instruction set architecture (ISA).<ref>J. Smith and R. Nair. Virtual Machines: Versatile Platforms for Systems and Processes (The Morgan Kaufmann Series in Computer Architecture and Design). Morgan Kaufmann Publishers Inc., 2005.</ref>
* With firmware-managed TLBs, a TLB miss causes a trap to system firmware, which is responsible for walking the page tables and finding the appropriate page table entry, similarly to what a TLB miss handler does for a software-managed TLB.  With a firmware-managed TLB, the format of the TLB entries is not visible to system software and can change from CPU to CPU without causing loss of compatibility for the operating system.

The [[MIPS architecture]] specifies a software-managed TLB.<ref>{{Cite web | url=http://www.eecs.harvard.edu/~mdw/course/cs161/handouts/mips.html | title=MIPS r2000/r3000 Architecture | access-date=16 November 2008 | last=Welsh | first=Matt | quote=If no matching TLB entry is found, a TLB miss exception occurs | url-status=dead | archive-url=https://web.archive.org/web/20081014061949/http://www.eecs.harvard.edu/~mdw/course/cs161/handouts/mips.html | archive-date=14 October 2008 | df=dmy-all }}</ref>

The [[SPARC V9]] architecture allows an implementation of SPARC V9 to have no MMU, an MMU with a software-managed TLB, or an MMU with a hardware-managed TLB,<ref>{{cite book|author=SPARC International, Inc.|title=The SPARC Architecture Manual, Version 9|url=http://sparc.org/technical-documents/#V9|publisher=[[Prentice Hall|PTR Prentice Hall]]}}</ref> and the UltraSPARC Architecture 2005 specifies a software-managed TLB.<ref>{{cite book|author=Sun Microsystems|title=UltraSPARC Architecture 2005|version=Draft D0.9.2, 19 June 2008|url=http://www.oracle.com/technetwork/systems/opensparc/1537734|publisher=Sun Microsystems|author-link=Sun Microsystems}}</ref>

The [[Itanium]] architecture provides an option of using either software- or hardware-managed TLBs.<ref>[http://www.informit.com/articles/article.aspx?p=29961&seqNum=4 Virtual Memory in the IA-64 Kernel > Translation Lookaside Buffer].</ref>

The [[DEC Alpha|Alpha]] architecture has a firmware-managed TLB, with the TLB miss handling code being in [[PALcode]], rather than in the operating system.  As the PALcode for a processor can be processor-specific and operating-system-specific, this allows different versions of PALcode to implement different page-table formats for different operating systems, without requiring that the TLB format, and the instructions to control the TLB, to be specified by the architecture.<ref>{{cite book|author=Compaq Computer Corporation|title=Alpha Architecture Handbook|version=Version 4|url=http://h18000.www1.hp.com/alphaserver/technology/literature/alphaahb.pdf|publisher=Compaq Computer Corporation|author-link=Compaq Computer Corporation|access-date=1 December 2010|archive-date=9 October 2014|archive-url=https://web.archive.org/web/20141009015236/http://h18000.www1.hp.com/alphaserver/technology/literature/alphaahb.pdf|url-status=dead}}</ref>