Editing VIA C7 (section)

==Design choices==
* C7 Esther as an evolutionary step after C3 Nehemiah, in which VIA / Centaur followed their traditional approach of balancing performance against a constrained transistor / power budget.
* The cornerstone of the C3 series chips' design philosophy has been that even a relatively simple in-order scalar core can offer reasonable performance against a complex superscalar out-of-order core if supported by an efficient "front-end", i.e. prefetch, cache and [[branch prediction]] mechanisms.
* In the case of C7, the design team have focused on further streamlining the (front-end) of the chip, i.e. cache size, associativity and throughput as well as the prefetch system.<ref>{{cite web | title = Detailed Platform Analysis in RightMark Memory Analyzer. Part 12: VIA C7/C7-M Processors| publisher = Pricenfees.com| url =https://www.pricenfees.com/digit-life-archives/via-cyrix-iii-samuel-2-600-667-mhz | access-date = 2007-03-12}}</ref>  At the same time no significant changes to the execution core (back-end) of the chip.
* The C7 successfully further closes the gap in performance with AMD / Intel chips, since clock speed is not thermally constrained.{{Citation needed|date=January 2009}}