Editing Very-large-scale integration (section)

== Structured design ==
Structured VLSI design is a modular methodology originated by [[Carver Mead]] and [[Lynn Conway]] for saving microchip area by minimizing the interconnect fabric area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using [[wiring by abutment]]. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting.<ref name="Digital Electronics - A Modern Approach by B K Jain">{{Cite book |last=Jain |first=B. K. |url=https://books.google.com/books?id=R5XBozPiTHAC&q=structured%20vlsi%20design%20hierarchical%20nesting&pg=PA159 |title=Digital Electronics - A Modern Approach by B K Jain |date=August 2009 |publisher=Global Vision Publishing House |isbn=9788182202153 |access-date=2 May 2017}}</ref>

Structured VLSI design had been popular in the early 1980s, but lost its popularity later{{Citation needed|date = November 2019}} because of the advent of [[placement and routing]] tools wasting a lot of area by [[Routing (electronic design automation)|routing]], which is tolerated because of the progress of [[Moore's law]]. When introducing the [[hardware description language]] KARL in the mid-1970s, [[Reiner Hartenstein]] coined the term "structured VLSI design" (originally as "structured LSI design"), echoing [[Edsger Dijkstra]]'s [[structured programming]] approach by procedure nesting to avoid chaotic ''spaghetti-structured'' programs.