Editing Very long instruction word (section)

== Implementations ==

[[Cydrome]] was a company producing VLIW numeric processors using [[emitter-coupled logic]] (ECL) integrated circuits in the same timeframe (late 1980s). This company, like Multiflow, failed after a few years.

One of the licensees of the Multiflow technology is [[Hewlett-Packard]], which [[Josh Fisher]] joined after Multiflow's demise. [[Bob Rau]], founder of Cydrome, also joined HP after Cydrome failed. These two would lead computer architecture research at Hewlett-Packard during the 1990s.

Along with the above systems, during the same time (1989–1990), Intel implemented VLIW in the [[Intel i860]], their first 64-bit microprocessor, and the first processor to implement VLIW on one chip.<ref name="nxp">{{Cite web| url=http://www.nxp.com/acrobat_download2/other/vliw-wp.pdf |archive-url=https://web.archive.org/web/20110929113559/http://www.nxp.com/acrobat_download2/other/vliw-wp.pdf |title=An Introduction To Very-Long Instruction Word (VLIW) Computer Architecture |archive-date=2011-09-29 |publisher=Philips Semiconductors}}</ref> This processor could operate in both simple RISC mode and VLIW mode:
<blockquote>
In the early 1990s, Intel introduced the i860 RISC microprocessor. This simple chip had two modes of operation: a scalar mode and a VLIW mode. In the VLIW mode, the processor always fetched two instructions and assumed that one was an integer instruction and the other floating-point.<ref name="nxp"/>
</blockquote>

The i860's VLIW mode was used extensively in [[Embedded system|embedded]] [[digital signal processor]] (DSP) applications since the application execution and datasets were simple, well ordered and predictable, allowing designers to fully exploit the parallel execution advantages enabled by VLIW. In VLIW mode, the i860 could maintain floating-point performance in the range of 20-40 double-precision MFLOPS; a very high value for its time and for a processor running at 25-50Mhz.

In the 1990s, Hewlett-Packard researched this problem as a side effect of ongoing work on their [[PA-RISC]] processor family. They found that the CPU could be greatly simplified by removing the complex dispatch logic from the CPU and placing it in the compiler. Compilers of the day were far more complex than those of the 1980s, so the added complexity in the compiler was considered to be a small cost.

VLIW CPUs are usually made of multiple RISC-like [[execution unit]]s that operate independently. Contemporary VLIWs usually have four to eight main execution units. Compilers generate initial instruction sequences for the VLIW CPU in roughly the same manner as for traditional CPUs, generating a sequence of RISC-like instructions. The compiler analyzes this code for dependence relationships and resource requirements. It then schedules the instructions according to those constraints. In this process, independent instructions can be scheduled in parallel. Because VLIWs typically represent instructions scheduled in parallel with a longer instruction word that incorporates the individual instructions, this results in a much longer [[opcode]] (termed ''very long'') to specify what executes on a given cycle.

Examples of contemporary VLIW CPUs include the [[TriMedia (mediaprocessor)|TriMedia]] media processors by [[NXP Semiconductors|NXP]] (formerly Philips Semiconductors), the [[Super Harvard Architecture Single-Chip Computer]] (SHARC) DSP by Analog Devices, the [[ST200 family]] by STMicroelectronics based on the Lx architecture (designed in Josh Fisher's HP lab by Paolo Faraboschi), the [[FR-V]] from [[Fujitsu]], the BSP15/16<ref name="pixelworks">{{cite web |url=http://www.pixelworks.com/ |archive-url=https://web.archive.org/web/19961224073554/http://www.pixelworks.com/ |archive-date=1996-12-24 |url-status=dead |title=Pixelworks &#124; BSP15/16 |access-date=2016-07-28 }}</ref> from [[Pixelworks]], the [[CEVA-X DSP]] from CEVA, the [[Jazz DSP]] from Improv Systems, the HiveFlex<ref>{{cite web |title=silicon hive Products |url=http://www.siliconhive.com/Flex/Site/Page.aspx?SectionID=867&Lang=UK |website=Silicon Hive |publisher=Silicon Hive BV |access-date=2012-01-28 |archive-url=https://web.archive.org/web/20120128101047/http://www.siliconhive.com/Flex/Site/Page.aspx?SectionID=867&Lang=UK |archive-date=2012-01-28 |url-status=dead}}</ref> series from Silicon Hive, and the MPPA Manycore family by Kalray. The Texas Instruments [[TMS320]] [[Digital signal processor|DSP]] line has evolved, in its [[Texas Instruments TMS320#C6000 series|C6000]] family, to look more like a VLIW, in contrast to the earlier [[Texas Instruments TMS320#C5000 series|C5000]] family. One or more [[Qualcomm Hexagon]]s can be found in most cell phones today. These contemporary VLIW CPUs are mainly successful as embedded media processors for consumer electronic devices.

VLIW features have also been added to configurable processor cores for [[system-on-a-chip]] (SoC) designs. For example, Tensilica's [[Xtensa]] LX2 processor incorporates a technology named Flexible Length Instruction eXtensions (FLIX) that allows multi-operation instructions. The Xtensa C/C++ compiler can freely intermix 32- or 64-bit FLIX instructions with the Xtensa processor's one-operation RISC instructions, which are 16 or 24 bits wide. By packing multiple operations into a wide 32- or 64-bit instruction word and allowing these multi-operation instructions to intermix with shorter RISC instructions, FLIX allows SoC designers to realize VLIW's performance advantages while eliminating the [[code bloat]] of early VLIW architectures.
The Infineon Carmel DSP is another VLIW processor core intended for SoC. It uses a similar code density improvement method called ''configurable long instruction word'' (CLIW).<ref name="eembc">{{cite web|url=http://www.eembc.org/press/pressrelease/020313.htm |title=EEMBC Publishes Benchmark Scores for Infineon Technologies' Carmel - DSP Core and TriCore - TC11IB Microcontroller |publisher=eembc.org|access-date=2016-07-28}}</ref>

Outside embedded processing markets, Intel's [[Itanium]] IA-64 [[explicitly parallel instruction computing]] (EPIC) and [[Elbrus 2000]] appear as the only examples of a widely used VLIW CPU architectures. However, EPIC architecture is sometimes distinguished from a pure VLIW architecture, since EPIC advocates full instruction predication, rotating register files, and a very long instruction word that can encode non-parallel instruction groups. VLIWs also gained significant consumer penetration in the [[graphics processing unit]] (GPU) market, though both [[Nvidia]] and [[AMD]] have since moved to RISC architectures to improve performance on non-graphics workloads.

[[ATI Technologies]]' (ATI) and [[Advanced Micro Devices]]' (AMD) [[TeraScale (microarchitecture)|TeraScale]] microarchitecture for [[graphics processing unit]]s (GPUs) is a VLIW microarchitecture.

In December 2015, the first shipment of PCs based on VLIW CPU [[Elbrus-2S+|Elbrus-4s]] was made in Russia.<ref name="tass">{{cite web|url=http://tass.ru/ekonomika/2498729|title=ТАСС|publisher=tass.ru|access-date=2016-07-28}}</ref>

The Neo by REX Computing is a processor consisting of a 2D mesh of VLIW cores aimed at power efficiency.<ref>{{cite web |title=The Tiny Chip That Could Disrupt Exascale Computing |url=https://www.nextplatform.com/2015/03/12/the-little-chip-that-could-disrupt-exascale-computing/ |website=The Next Platform |date=12 March 2015 |publisher=Stackhouse Publishing Inc |access-date=26 April 2021}}</ref>

The [[Elbrus 2000]] ({{langx|ru|Эльбрус 2000}}) and its successors are Russian 512-bit wide VLIW microprocessors developed by [[Moscow Center of SPARC Technologies]] (MCST) and fabricated by [[TSMC]].