Editing Virtual 8086 mode (section)

=={{anchor|VME}}Virtual-8086 mode extensions (VME)==
The Pentium architecture added a number of enhancements to the virtual 8086 mode. These were however documented by Intel only starting with the subsequent [[P6 (microarchitecture)]];<ref name="Shanley1998">{{cite book|author=T. Shanley|title=Pentium Pro and Pentium II System Architecture|url=https://books.google.com/books?id=MLJClvCYh34C&pg=PA427|year=1998|publisher=Addison-Wesley |isbn=978-0-201-30973-7|pages=427, 465–480}}</ref> their more recent formal name is Virtual-8086 Mode Extensions, abbreviated VME<ref>{{cite book|url=https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide.html|title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3 (3A, 3B, 3C & 3D): System Programming Guide|page=2{{hyphen}}17|publisher=[[Intel]]|date=May 2020}}</ref> (older documentation may use "Virtual 8086 mode enhancements" as the VME acronym expansion).<ref name="Shanley1998"/> Some later Intel 486 chips also support it.<ref>{{cite web|url=http://www.gossamer-threads.com/lists/linux/kernel/585146?do=post_view_threaded#585146 |title=Mailing List Archive: Re: 2.6.14: CR4 not needed to be inspected on the 486 anymore? |publisher=Gossamer-threads.com |access-date=2014-02-20}}</ref><ref name="pvi1">{{cite web|url=http://www.rcollins.org/articles/pvi1/pvi1.html |title=Pentium Protected Mode Virtual Interrupts (PVI) |publisher=Rcollins.org |access-date=2014-02-20}}</ref> The enhancements address mainly the 8086 virtualization overhead, with a particular focus on (virtual) interrupts.<ref name="Shanley1998"/><ref>{{cite web|url=http://www.rcollins.org/articles/vme1/ |title=Virtual Mode Extensions on the Pentium Processor |publisher=Rcollins.org |access-date=2014-02-20}}</ref> Before the extensions were publicly documented in the P6 documentation, the official documentation referred to the famed [[Appendix H]], which was omitted from the public documentation and shared only with selected partners under [[Non-disclosure agreement|NDA]].

Activating VME is done by setting bit number 0 (0x1 in value) of [[control register#CR4|CR4]]. Because the VME interrupt speed-up enhancements were found useful for non-VM86 protected tasks, they can also be enabled separately by setting only bit number 1 (0x2 in value), which is called PVI (Protected Mode Virtual Interrupts).<ref name="Shanley1998"/><ref name="pvi1"/> Detecting whether a processor supports VME (including PVI) is done using the [[CPUID]] instruction, with an initial EAX value of 0x1, by testing the value of second bit (bit number 1, 0x2 in value) in EDX register, which is set if VME is supported by the processor.<ref>{{cite book|url=https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-2a-2b-2c-and-2d-instruction-set-reference-a-z.html|title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (2A, 2B, 2C & 2D): Instruction Set Reference, A-Z|pages=3{{hyphen}}199,3{{hyphen}}221,3{{hyphen}}222|publisher=[[Intel]]|date=May 2020}}</ref><ref name="Shanley1998"/> In Linux, this latter bit is reported as the {{mono|vme}} [[CPU flag (x86)|flag]] in the {{mono|/proc/[[cpuinfo]]}} file, under the "flags" section.

In virtual 8086 mode, the basic idea is that when IOPL is less than 3, PUSHF/POPF/STI/CLI/INT/IRET instructions will treat the value of VIF in the real 32-bit EFLAGS register as the value of IF in the simulated 16-bit FLAGS register (32-bit PUSHFD/POPFD continues to GP fault). VIP will cause a GP fault on the setting of simulated IF, directing the OS to process any pending interrupts. PVI is the same idea but only affects CLI/STI instructions.

First generation [[AMD Ryzen]] CPUs have been found to feature a broken VME implementation.<ref>{{cite web|url=http://www.os2museum.com/wp/vme-broken-on-amd-ryzen/|title=VME Broken on AMD Ryzen|date=May 12, 2017|author=Michal Necasek|website=OS/2 Museum}}</ref> The second generation Ryzen (2000 series) has fixed this issue.<ref>{{cite web|url=https://support.amd.com/TechDocs/55449_Fam_17h_M_00h-0Fh_Rev_Guide.pdf|title=Revision Guide for AMD Family 17h Models 00h-0Fh Processors|date=June 2018|website=[[Advanced Micro Devices|AMD]]}}</ref>