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WinChip
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===Later developments=== WinChip 2, an update of C6, retained the simple in-order execution pipeline of its predecessor, but added dual MMX/3DNow! processing units that could operate in superscalar execution.<ref name="WinChip2DataSheet" /> This made it the only non-AMD CPU on Socket 7 to support 3DNow! instructions. WinChip 2A added [[CPU multiplier|fractional multiplier]]s and adopted a 100 MHz [[front side bus]] to improve memory access and L2 cache performance.<ref>{{cite web |last=Hare |first=Chris |url=http://users.erols.com/chare/cpuspeed.htm |title=Processor Speed Settings |accessdate=24 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070428051306/http://users.erols.com/chare/cpuspeed.htm |archivedate=28 April 2007 }}</ref> It also adopted a [[PR rating|performance rating]] nomenclature instead of reporting the real clock speed, similar to contemporary AMD and [[Cyrix]] processors. Another revision, the WinChip 2B, was also planned. This featured a die shrink to 0.25 ΞΌm, but was only shipped in limited numbers.<ref name=WinChipSandpile>{{cite web |url=http://www.sandpile.org/impl/c2.htm |title=IA-32 implementation: Centaur WinChip 2 |work=SandPile.org |accessdate=29 April 2007 |url-status=dead |archiveurl=https://web.archive.org/web/20070427100243/http://sandpile.org/impl/c2.htm |archivedate=27 April 2007 }}</ref> A third model, the WinChip 3, was planned as well. This was meant to receive a doubled L1 cache, but the W3 CPU never made it to market.<ref name=WinChipSandpile />
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