Editing AVR microcontrollers (section)

== FPGA clones ==
With the growing popularity of [[Field-programmable gate array|FPGAs]] among the open source community, people have started developing open source processors compatible with the AVR instruction set. The [[OpenCores]] website lists the following major AVR clone projects:

* pAVR,<ref>{{cite web|url=http://opencores.org/project,pavr|title=pAVR :: Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[VHDL]], is aimed at creating the fastest and maximally featured AVR processor, by implementing techniques not found in the original AVR processor such as deeper pipelining.
* avr_core,<ref>{{cite web|url=http://opencores.org/project,avr_core|title=AVR Core :: Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[VHDL]], is a clone aimed at being as close as possible to the ATmega103.
* Navré,<ref>{{cite web|url=http://opencores.org/project,navre|title=Navré AVR clone (8-bit RISC) Overview|publisher=OpenCores|access-date=2012-09-19}}</ref> written in [[Verilog]], implements all [[Atmel AVR instruction set|Classic Core]] instructions and is aimed at high performance and low resource usage. It does not support [[interrupt]]s.
* softavrcore,<ref>{{cite web|url=https://opencores.org/projects/softavrcore|title=Soft AVR Core + Interfaces Overview|publisher=OpenCores|access-date=2020-06-16}}</ref> written in [[Verilog]], implements the [[AVR instruction set]] up to AVR5, supports interrupts along with optional automatic interrupt acknowledgement, power saving via [[Idle (CPU)|sleep mode]] plus some peripheral interfaces and [[Hardware acceleration|hardware accelerators]] (such as [[UART]], [[Serial Peripheral Interface|SPI]], [[cyclic redundancy check]] calculation unit and [[Programmable interval timer|system timers]]). These peripherals demonstrate how could these be attached to and configured for this core. Within the package, a full-featured [[FreeRTOS]] port is also available as an example for the core + peripheral utilization.
* The opencores project CPU lecture<ref>{{cite web|url=http://opencores.org/project,cpu_lecture|title=CPU lecture|publisher=OpenCores|access-date=2015-02-16}}</ref> written in [[VHDL]] by Dr. Jürgen Sauermann explains in detail how to design a complete AVR-based [[system on a chip]] (SoC).