Editing Foreach loop (section)

=== SystemVerilog ===
[[SystemVerilog]] supports iteration over any vector or array type of any dimensionality using the <code>foreach</code> keyword.

A trivial example iterates over an array of integers:

{| class="wikitable"
! code !! prints
|-
|
<syntaxhighlight lang="systemverilog">
int  array_1d[] = '{ 3, 2, 1, 0 };

foreach array_1d[index]
  $display("array_1d[%0d]: %0d", index, array_1d[index]);
</syntaxhighlight>
|
 array_1d[0]: 3
 array_1d[1]: 2
 array_1d[2]: 1
 array_1d[3]: 0
|}

A more complex example iterates over an associative array of arrays of integers:

{| class="wikitable"
! code !! prints
|-
|
<syntaxhighlight lang="systemverilog">
int  array_2d[string][] = '{ "tens": '{ 10, 11 },
                             "twenties": '{ 20, 21 } };

foreach array_2d[key,index]
  $display("array_2d[%s,%0d]: %0d", key, index, array_2d[key,index]);
</syntaxhighlight>
|
 array_2d[tens,0]: 10
 array_2d[tens,1]: 11
 array_2d[twenties,0]: 20
 array_2d[twenties,1]: 21
|}