Editing CPU cache (section)

====In x86 microprocessors====
[[File:Motherboard Intel 386.jpg|thumb|upright=1.2|Example of a motherboard with an [[i386]] microprocessor (33&nbsp;MHz), 64&nbsp;KiB cache (25&nbsp;ns; 8 chips in the bottom left corner), 2&nbsp;MiB DRAM (70&nbsp;ns; 8 [[SIMM]]s to the right of the cache), and a cache controller ([[Austek Microsystems|Austek]] A38202; to the right of the processor)]]
As the [[x86]] microprocessors reached clock rates of 20&nbsp;MHz and above in the [[Intel 80386|386]], small amounts of fast cache memory began to be featured in systems to improve performance. This was because the [[DRAM]] used for main memory had significant latency, up to 120&nbsp;ns, as well as refresh cycles. The cache was constructed from more expensive, but significantly faster, [[static random-access memory|SRAM]] [[Memory cell (computing)|memory cells]], which at the time had latencies around 10–25&nbsp;ns. The early caches were external to the processor and typically located on the motherboard in the form of eight or nine [[Dual in-line package|DIP]] devices placed in sockets to enable the cache as an optional extra or upgrade feature.

Some versions of the Intel 386 processor could support 16 to 256&nbsp;KiB of external cache.

With the [[Intel 80486|486]] processor, an 8&nbsp;KiB cache was integrated directly into the CPU die. This cache was termed Level 1 or L1 cache to differentiate it from the slower on-motherboard, or Level 2 (L2) cache. These on-motherboard caches were much larger, with the most common size being 256&nbsp;KiB. There were some system boards that contained sockets for the Intel 485Turbocache [[Expansion_card#Daughterboard|daughtercard]] which had either 64 or 128 Kbyte of cache memory.<ref>Chen, Allan, "The 486 CPU: ON A High-Performance Flight Vector", Intel Corporation, Microcomputer Solutions, November/December 1990, p. 2</ref><ref>Reilly, James, Kheradpir, Shervin, "An Overview of High-performance Hardware Design Using the 486 CPU", Intel Corporation, Microcomputer Solutions, November/December 1990, page 20</ref> The popularity of on-motherboard cache continued through the [[Intel P5|Pentium MMX]] era but was made obsolete by the introduction of [[SDRAM]] and the growing disparity between bus clock rates and CPU clock rates, which caused on-motherboard cache to be only slightly faster than main memory.

The next development in cache implementation in the x86 microprocessors began with the [[Pentium Pro]], which brought the secondary cache onto the same package as the microprocessor, clocked at the same frequency as the microprocessor.

On-motherboard caches enjoyed prolonged popularity thanks to the [[AMD K6-2]] and [[AMD K6-III]] processors that still used [[Socket 7]], which was previously used by Intel with on-motherboard caches. K6-III included 256&nbsp;KiB on-die L2 cache and took advantage of the on-board cache as a third level cache, named L3 (motherboards with up to 2&nbsp;MiB of on-board cache were produced). After the Socket&nbsp;7 became obsolete, on-motherboard cache disappeared from the x86 systems.

The three-level caches were used again first with the introduction of multiple processor cores, where the L3 cache was added to the CPU die. It became common for the total cache sizes to be increasingly larger in newer processor generations, and recently (as of 2011) it is not uncommon to find Level 3 cache sizes of tens of megabytes.<ref>{{cite web
 | url = http://ark.intel.com/products/family/59139/Intel-Xeon-Processor-E7-Family/server
 | title = Intel Xeon Processor E7 Family
 | work = Intel® ARK (Product Specs)
 | access-date = 2013-10-10
 | publisher = [[Intel]]
}}</ref>

[[Intel]] introduced a Level 4 on-package cache with the [[Haswell (microarchitecture)|Haswell]] [[microarchitecture]]. ''[[Crystalwell]]''<ref name="intel-ark-crystal-well" /> Haswell CPUs, equipped with the [[GT3e]] variant of Intel's integrated Iris Pro graphics, effectively feature 128&nbsp;MiB of embedded DRAM ([[eDRAM]]) on the same package. This L4 cache is shared dynamically between the on-die GPU and CPU, and serves as a [[victim cache]] to the CPU's L3 cache.<ref name="anandtech-i74950hq" />