Editing CPU cache (section)

====Current research====
Early cache designs focused entirely on the direct cost of cache and [[random-access memory|RAM]] and average execution speed.
More recent cache designs also consider [[low-power electronics|energy efficiency]], fault tolerance, and other goals.<ref>{{cite journal
 |url=https://spectrum.ieee.org/chip-design-thwarts-sneak-attack-on-data
 |title=Chip Design Thwarts Sneak Attack on Data
 |author=Sally Adee
 |date=November 2009
 |journal=[[IEEE Spectrum]]
 |volume=46
 |issue=11
 |page=16
 |doi=10.1109/MSPEC.2009.5292036
|s2cid=43892134
 |url-access=subscription
 }}</ref><ref>{{cite conference |last1=Wang |first1=Zhenghong |last2=Lee |first2=Ruby B. |date=November 8–12, 2008 |title=A novel cache architecture with enhanced performance and security |url=http://palms.princeton.edu/system/files/Micro08_Newcache.pdf |conference=41st annual IEEE/ACM International Symposium on Microarchitecture |pages=83–93 |archive-url=https://web.archive.org/web/20120306225926/http://palms.princeton.edu/system/files/Micro08_Newcache.pdf |archive-date=March 6, 2012 |url-status=live}}</ref>

There are several tools available to computer architects to help explore tradeoffs between the cache cycle time, energy, and area; the CACTI cache simulator<ref>{{cite web|url=https://www.hpl.hp.com/research/cacti/ |title=CACTI |website=HP Labs |access-date=2023-01-29}}</ref> and the SimpleScalar instruction set simulator are two open-source options.