Editing Adder (electronics) (section)

===Adders supporting multiple bits===
====Ripple-carry adder====
[[File:4-bit ripple carry adder.svg|thumb|4-bit adder with logical block diagram shown|alt=4-bit adder with logical block diagram shown]]
[[File:RippleCarry2.gif|thumb|Decimal 4-digit ripple carry adder. FA = full adder, HA = half adder.]]

It is possible to create a logical circuit using multiple full adders to add ''N''-bit numbers. Each full adder inputs a <math>C_{in}</math>, which is the <math>C_{out}</math> of the previous adder. This kind of adder is called a '''ripple-carry adder''' (RCA), since each carry bit "ripples" to the next full adder. The first (and only the first) full adder may be replaced by a half adder (under the assumption that <math>C_{in} = 0</math>).

The layout of a ripple-carry adder is simple, which allows fast design time; however, the ripple-carry adder is relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The [[gate delay]] can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic. In a 32-bit ripple-carry adder, there are 32 full adders, so the critical path (worst case) delay is 3 (from input to <math>C_{out}</math> of first adder) + 31 × 2 (for carry propagation in latter adders) = 65 gate delays.<ref name="Adder"/>
The general equation for the worst-case delay for a ''n''-bit carry-ripple adder, accounting for both the sum and carry bits, is:

:<math>T_\text{CRA}(n) = T_\text{HA} + (n-1) \cdot T_\text{c} + T_\text{s} = </math><math> T_\text{FA} + (n-1) \cdot T_c = </math><math> 3 D + (n-1) \cdot 2 D = (2n+1) \cdot D</math>

A design with alternating carry polarities and optimized [[AND-OR-Invert]] gates can be about twice as fast.<ref name="Burgess_2011"/><ref name="Fischer">{{Cite web|url=https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|title=Einfache Schaltungsblöcke|accessdate=2021-09-05|archive-url=https://web.archive.org/web/20210905175605/https://sus.ziti.uni-heidelberg.de/Lehre/WS1617_DST/DST_Fischer_06_Einfache_Bloecke_FF.pptx.pdf|archive-date=2021-09-05|last=Fischer|first=P.|publisher=Universität Heidelberg}}</ref>

====Carry-lookahead adder (Weinberger and Smith, 1958)====

{{main|Carry-lookahead adder}}
[[File:4-bit carry lookahead adder.svg|thumb|4-bit adder with carry lookahead]]
[[File:64-bit lookahead carry unit.svg|thumb|64-bit adder with carry lookahead]]

To reduce the computation time, Weinberger and Smith invented a faster way to add two binary numbers by using [[carry-lookahead adder]]s (CLA).<ref>{{cite journal |first1=A. |last1=Weinberger |first2=J.L. |last2=Smith |title=A Logic for High-Speed Addition |journal=Nat. Bur. Stand. Circ. |issue=591 |pages=3–12 |date=1958 |publisher=National Bureau of Standards |url=https://nvlpubs.nist.gov/nistpubs/Legacy/circ/nbscircular591.pdf}}</ref> They introduced two signals (<math>P</math> and <math>G</math>) for each bit position, based on whether a carry is propagated through from a less significant bit position (at least one input is a 1), generated in that bit position (both inputs are 1), or killed in that bit position (both inputs are 0).  In most cases, <math>P</math> is simply the sum output of a half adder and <math>G</math> is the carry output of the same adder.  After <math>P</math> and <math>G</math> are generated, the carries for every bit position are created.

Mere derivation of Weinberger-Smith CLA recurrence, are: [[Brent–Kung adder]] (BKA),<ref name="Brent-Kung_1982"/> and the [[Kogge–Stone adder]] (KSA).<ref name="Kogge-Stone_1973"/><ref name="ULVD_2015"/>
This was shown in  Oklobdzija and Zeydel paper in IEEE Journal of Solid-State Circuits.<ref>{{cite journal |first1=B.R. |last1=Zeydel |first2=D. |last2=Baran |first3=V.G. |last3=Oklobdzija |title=Energy Efficient Design of High-Performance VLSI Adders |journal=IEEE Journal of Solid-State Circuits |volume=45 |issue=6 |pages=1220–33 |date=June 2010 |doi=10.1109/JSSC.2010.2048730 |url=https://www.acsel-lab.com/Publications/Papers/energy_efficient_adders.pdf}}</ref>

Some other multi-bit adder architectures break the adder into blocks.  It is possible to vary the length of these blocks based on the [[propagation delay]] of the circuits to optimize computation time.  These block based adders include the [[carry-skip adder|carry-skip (or carry-bypass) adder]] which will determine <math>P</math> and <math>G</math> values for each block rather than each bit, and the [[carry-select adder]] which pre-generates the sum and carry values for either possible carry input (0 or 1) to the block, using multiplexers to select the appropriate result ''when'' the carry bit is known.

By combining multiple carry-lookahead adders, even larger adders can be created. This can be used at multiple levels to make even larger adders. For example, the following adder is a 64-bit adder that uses four 16-bit CLAs with two levels of [[lookahead carry unit]]s.

Other adder designs include the [[carry-select adder]], [[conditional sum adder]], [[carry-skip adder]], and carry-complete adder.

====Carry-save adders====
{{main|Carry-save adder}}

If an adding circuit is to compute the sum of three or more numbers, it can be advantageous to not propagate the carry result. Instead, three-input adders are used, generating two results: a sum and a carry. The sum and the carry may be fed into two inputs of the subsequent 3-number adder without having to wait for propagation of a carry signal. After all stages of addition, however, a conventional adder (such as the ripple-carry or the lookahead) must be used to combine the final sum and carry results.