Editing Branch predictor (section)

===Next line prediction===
Some [[superscalar processor]]s (MIPS [[R8000]], [[Alpha 21264]], and [[Alpha 21464]] (EV8)) fetch each line of instructions with a pointer to the next line. This next-line predictor handles [[branch target predictor|branch target prediction]] as well as branch direction prediction.

When a next-line predictor points to aligned groups of 2, 4, or 8 instructions, the branch target will usually not be the first instruction fetched, and so the initial instructions fetched are wasted. Assuming for simplicity, a uniform distribution of branch targets, 0.5, 1.5, and 3.5 instructions fetched are discarded, respectively.

Since the branch itself will generally not be the last instruction in an aligned group, instructions after the taken branch (or its [[delay slot]]) will be discarded. Once again, assuming a uniform distribution of branch instruction placements, 0.5, 1.5, and 3.5 instructions fetched are discarded.

The discarded instructions at the branch and destination lines add up to nearly a complete fetch cycle, even for a single-cycle next-line predictor.