Editing Bus (computing) (section)

==Implementation details==
Buses can be [[parallel bus]]es, which carry [[data word]]s in parallel on multiple wires, or [[serial bus]]es, which carry data in bit-serial form. The addition of extra power and control connections, [[differential signaling|differential driver]]s, and data connections in each direction usually means that most serial buses have more conductors than the minimum of one used in [[1-Wire]] and [[UNI/O]]. As data rates increase, the problems of [[timing skew]], power consumption, electromagnetic interference and [[crosstalk]] across parallel buses become more and more difficult to circumvent. One partial solution to this problem has been to [[double pump]] the bus. Often, a serial bus can be operated at higher overall data rates than a parallel bus, despite having fewer electrical connections, because a serial bus inherently has no timing skew or crosstalk. [[USB]], [[FireWire]], and [[Serial ATA]] are examples of this. [[Multidrop]] connections do not work well for fast serial buses, so most modern serial buses use [[Daisy chain (information technology)#Computer hardware|daisy-chain]] or hub designs.

The transition from parallel to serial buses was allowed by [[Moore's law]] which allowed for the incorporation of [[SerDes]] in integrated circuits which are used in computers.<ref>{{cite book | url=https://books.google.com/books?id=aUCgNOpyUbgC&dq=parallel++serial++serdes+moore%27s+law&pg=PA275 | isbn=978-1-4020-7496-7 | title=The Boundary — Scan Handbook | date=30 June 2003 | publisher=Springer }}</ref>

[[computer network|Network]] connections such as [[Ethernet]] are not generally regarded as buses, although the difference is largely conceptual rather than practical. An attribute generally used to characterize a bus is that power is provided by the bus for the connected hardware. This emphasizes the [[busbar]] origins of bus architecture as supplying switched or distributed power. This excludes, as buses, schemes such as serial [[RS-232]], parallel [[Centronics]], [[IEEE 1284]] interfaces and Ethernet, since these devices also needed separate power supplies. [[Universal Serial Bus]] devices may use the bus supplied power, but often use a separate power source. This distinction is exemplified by a [[Plain old telephone service|telephone]] system with a connected [[modem]], where the [[RJ11]] connection and associated modulated signalling scheme is not considered a bus, and is analogous to an [[Ethernet]] connection. A phone line connection scheme is not considered to be a bus with respect to signals, but the [[telephone exchange|Central Office]] uses buses with [[cross-bar switch]]es for connections between phones.

However, this distinction{{mdashb}}that power is provided by the bus{{mdashb}}is not the case in many [[avionics|avionic systems]], where data connections such as [[ARINC 429]], [[ARINC 629]], [[MIL-STD-1553B]] (STANAG 3838), and EFABus ([[STANAG 3910]]) are commonly referred to as ''data buses'' or, sometimes, ''databuses''. Such [[avionics#Aircraft networks|avionic data buses]] are usually characterized by having several [[Line-replaceable unit|Line Replaceable Items/Units]] (LRI/LRUs) connected to a common, shared [[Media (communication)|media]]. They may, as with ARINC 429, be [[Simplex communication|simplex]], i.e. have a single source LRI/LRU or, as with ARINC 629, MIL-STD-1553B, and STANAG 3910, be [[Duplex (telecommunications)|duplex]], allow all the connected LRI/LRUs to act, at different times ([[half duplex]]), as transmitters and receivers of data.<ref name="ASSC 2003">Avionic Systems Standardisation Committee, ''Guide to Digital Interface Standards For Military Avionic Applications'', ASSC/110/6/2, Issue 2, September 2003</ref>

The frequency or the speed of a bus is measured in Hz such as MHz and determines how many clock cycles there are per second; there can be one or more data transfers per clock cycle. If there is a single transfer per clock cycle it is known as [[Single Data Rate]] (SDR), and if there are two transfers per clock cycle it is known as [[Double Data Rate]] (DDR) although the use of signalling other than SDR is uncommon outside of RAM. An example of this is PCIe which uses SDR.<ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> Within each data transfer there can be multiple bits of data. This is described as the width of a bus which is the number of bits the bus can transfer per clock cycle and can be synonymous with the number of physical electrical conductors the bus has if each conductor transfers one bit at a time.<ref>{{cite book | url=https://books.google.com/books?id=hDwDEAAAQBAJ&dq=bus+width&pg=PA54 | isbn=978-1-000-11716-5 | title=Foundations of Computer Technology | date=25 October 2020 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=j0wsBgAAQBAJ&dq=computer+bus+frequency&pg=PA39 | title=PC Systems, Installation and Maintenance | isbn=978-1-136-37442-5 | last1=Beales | first1=R. P. | date=11 August 2006 | publisher=Routledge }}</ref><ref>{{cite web | url=https://computer.howstuffworks.com/motherboard4.htm#:~:text=Bus%20speed%20usually%20refers%20to,dramatically%20affect%20a%20computer%27s%20performance | title=How Motherboards Work | date=20 July 2005 }}</ref> The data rate in bits per second can be obtained by multiplying the number of bits per clock cycle times the frequency times the number of transfers per clock cycle.<ref>{{cite book | url=https://books.google.com/books?id=6FnMBQAAQBAJ&q=Data+rate&pg=PA92 | title=Computer Busses | isbn=978-1-4200-4168-2 | last1=Buchanan | first1=Bill | date=25 April 2000 | publisher=CRC Press }}</ref><ref>{{cite book | url=https://books.google.com/books?id=vpnJDwAAQBAJ&q=Width | title=The Computer Engineering Handbook | isbn=978-1-4398-3316-2 | last1=Oklobdzija | first1=Vojin G. | date=5 July 2019 | publisher=CRC Press }}</ref> Alternatively a bus such as [[PCIe]] can use modulation or encoding such as [[PAM4]]<ref>{{Cite web |last=Robinson |first=Dan |date=2022-01-12 |title=Final PCIe 6.0 specs unleashed: 64 GTps link speed incoming... with products to follow in 2023 |url=https://www.theregister.com/2022/01/12/final_pcie_60_specs_released/ |website=www.theregister.com}}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref><ref>{{cite web | url=https://arstechnica.com/gadgets/2022/01/pci-express-6-0-spec-is-finalized-doubling-bandwidth-for-ssds-gpus-and-more/ | title=PCIe 5.0 is just beginning to come to new PCS, but version 6.0 is already here | date=12 January 2022 }}</ref> which groups 2 bits into symbols which are then transferred instead of the bits themselves, and allows for an increase in data transfer speed without increasing the frequency of the bus. The effective or real data transfer speed/rate may be lower due to the use of encoding that also allows for error correction such as 128/130b (b for bit) encoding.<ref>{{cite web | url=https://www.xda-developers.com/pcie-6/ | title=PCIe 6.0: Everything you need to know about the upcoming standard | date=30 June 2024 }}</ref><ref>{{cite web | url=https://semiengineering.com/knowledge_centers/communications-io/off-chip-communications/pam-4-signaling/ | title=PAM-4 Signaling }}</ref><ref>{{cite book | url=https://books.google.com/books?id=M_TKDwAAQBAJ&dq=pcie+rate&pg=PA155 | isbn=978-0-7384-5812-0 | title=IBM z15 (8561) Technical Guide | date=13 July 2022 | publisher=IBM Redbooks }}</ref> The data transfer speed is also known as the bandwidth.<ref>{{cite book | url=https://books.google.com/books?id=eV1_LjW3pTkC&dq=agp+2133&pg=PA304 | isbn=978-0-7897-2745-9 | title=Upgrading and Repairing PCS | date=2003 | publisher=Que }}</ref><ref>{{cite web | url=https://www.anandtech.com/show/21335/full-draft-of-pcie-70-spec-available-512-gbs-over-pcie-x16-incoming | title=PCIe 7.0 Draft 0.5 Spec Available: 512 GB/S over PCIe x16 on Track for 2025 }}</ref>

=== Bus multiplexing ===
{{main | Bus encoding#Other examples of bus encoding }}

The simplest [[system bus]] has completely separate input data lines, output data lines, and address lines.
To reduce cost, most microcomputers have a bidirectional data bus, re-using the same wires for input and output at different times.<ref name="typewriter" >
Don Lancaster.
[https://www.tinaja.com/ebooks/tvtcb.pdf "TV Typewriter Cookbook"]. ([[TV Typewriter]]).
Section "Bus Organization".
p. 82.
</ref>

Some processors use a dedicated wire for each bit of the address bus, data bus, and the control bus.
For example, the 64-pin [[STEbus]] is composed of 8 physical wires dedicated to the 8-bit data bus, 20 physical wires dedicated to the 20-bit address bus, 21 physical wires dedicated to the control bus, and 15 physical wires dedicated to various power buses.

Bus multiplexing requires fewer wires, which reduces costs in many early microprocessors and DRAM chips.
One common multiplexing scheme, [[#Address multiplexing|address multiplexing]], has already been mentioned.
Another multiplexing scheme re-uses the address bus pins as the data bus pins,<ref name="typewriter" /> an approach used by [[conventional PCI]] and the [[8086]].
The various ''serial buses'' can be seen as the ultimate limit of multiplexing, sending each of the address bits and each of the data bits, one at a time, through a single pin (or a single differential pair).