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CPU cache
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===Policies=== ===={{Anchor|EVICTION}}Replacement policies==== {{Main article|Cache replacement policies}} To make room for the new entry on a cache miss, the cache may have to evict one of the existing entries. The heuristic it uses to choose the entry to evict is called the replacement policy. The fundamental problem with any replacement policy is that it must predict which existing cache entry is least likely to be used in the future. Predicting the future is difficult, so there is no perfect method to choose among the variety of replacement policies available. One popular replacement policy, [[least-recently used]] (LRU), replaces the least recently accessed entry. Marking some memory ranges as non-cacheable can improve performance, by avoiding caching of memory regions that are rarely re-accessed. This avoids the overhead of loading something into the cache without having any reuse. Cache entries may also be disabled or locked depending on the context. ====Write policies==== {{Main article|Cache (computing)#WRITEPOLICIES|l1=Cache (computing) Β§ Writing policies}} If data are written to the cache, at some point they must also be written to main memory; the timing of this write is known as the write policy. In a [[write-through]] cache, every write to the cache causes a write to main memory. Alternatively, in a [[write-back]] or copy-back cache, writes are not immediately mirrored to the main memory, with locations been written over being marked as [[Dirty bit|dirty]], being written back to the main memory only when they are evicted from the cache. For this reason, a read miss in a write-back cache may sometimes require two memory accesses to service: one to first write the dirty location to main memory, and then another to read the new location from memory. Also, a write to a main memory location that is not yet mapped in a write-back cache may evict an already dirty location, thereby freeing that cache space for the new memory location. There are intermediate policies as well. The cache may be write-through, but the writes may be held in a store data queue temporarily, usually so multiple stores can be processed together (which can reduce bus turnarounds and improve bus utilization). Cached data from the main memory may be changed by other entities (e.g., peripherals using [[direct memory access]] (DMA) or another core in a [[multi-core processor]]), in which case the copy in the cache may become out-of-date or stale. Alternatively, when a CPU in a [[multiprocessor]] system updates data in the cache, copies of data in caches associated with other CPUs become stale. Communication protocols between the cache managers that keep the data consistent are known as [[cache coherence]] protocols.
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