Editing Celeron (section)

==== {{Anchor|Mendocino}}Mendocino ====
{{redirect|Mendocino (microprocessor)|the AMD mobile APU|List of AMD mobile processors#Mendocino (7020 series, Zen2/RDNA2 based)}}
[[Image:Intel Celeron 300A MHz.jpg|thumb|180px|right|Intel Celeron Mendocino 300&nbsp;MHz in SEPP package]]
[[Image:KL Intel Celeron Mendocino Top.jpg|thumb|150px|right|Top of a Mendocino-core Socket 370 Celeron (PPGA package)]] [[Image:KL Intel Celeron Mendocino S370.jpg|thumb|150px|right|Underside of a Mendocino-core Socket 370 Celeron, 333&nbsp;MHz]]
[[File:Intel Celeron 500MHz Mendocino SL3LQ (PNG).png|thumb|Intel Celeron 500MHz Mendocino die shot]]
The ''Mendocino'' Celeron, launched August 24, 1998, was the first retail CPU to use on-die [[L2 cache]]. Whereas Covington had no secondary cache at all, Mendocino included 128&nbsp;KB of L2 cache running at full clock rate. The first Mendocino-core Celeron was clocked at a then-modest 300&nbsp;MHz but offered almost twice the performance of the old cacheless Covington Celeron at the same clock rate. To distinguish it from the older Covington 300&nbsp;MHz, Intel called the Mendocino core Celeron ''300A''.<ref name="BigCPUShootout">{{cite news|last=Pabst|first=Thomas|title=Big CPU Shoot Out: Intel Launches New Celeron with Mendocino Core and Pentium II 450|url=http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|archive-url=https://archive.today/20130204153422/http://www.tomshardware.com/1998/08/24/big_cpu_shoot_out/|url-status=dead|archive-date=February 4, 2013|publisher=[[Tom's Hardware Guide]]|date=August 24, 1998|access-date=July 30, 2007}}</ref> Although the other Mendocino Celerons (the 333&nbsp;MHz part, for example) did not have an ''A'' appended, some people call all Mendocino processors ''Celeron-A'' regardless of clock rate.

The new Mendocino-core Celeron was a good performer from the outset. Indeed, most industry analysts regarded the first Mendocino-based Celerons as ''too'' successful—performance was sufficiently high to not only compete strongly with rival parts, but also to attract buyers away from Intel's high-profit flagship, the Pentium II. [[Overclocking|Overclockers]] soon discovered that, given a high-end [[motherboard]], many Celeron 300A CPUs could run reliably at 450&nbsp;MHz. This was achieved by simply increasing the [[front-side bus]] (FSB) clock rate from the stock 66&nbsp;MHz to the 100&nbsp;MHz clock of the [[Pentium II]], helped by several facts: the 440BX chipset with nominal support for 100&nbsp;MHz and correspondent memory had already been on the market, and the internal L2 cache was more tolerant to overclocking than external cache chips, which already had to run at half-CPU speed by design. At this frequency, the budget Mendocino Celeron rivaled the fastest x86 processors available.<ref name="BigCPUShootout" /> Some motherboards were designed to prevent this modification, by restricting the Celeron's front side bus to 66&nbsp;MHz. However, [[overclocking|overclockers]] soon found that putting tape over pin B21 of the Celeron's interface slot circumvented this, allowing a 100&nbsp;MHz bus.<ref>{{cite web|url=http://www.tomshardware.com/reviews/66-mhz-slot-1-cpus-running-100-mhz,66.html|title=How to Get All 66 MHz Slot 1 CPUs Running 100 MHz|author=Thomas Pabst|work=Tom's Hardware|date=May 14, 1998 }}</ref>

At the time on-die cache was difficult to manufacture; especially [[L2 cache|L2]] as more of it is needed to attain an adequate level of performance. A benefit of on-die cache is that it operates at the same clock rate as the CPU. All other Intel CPUs at that time used motherboard mounted or slot mounted secondary [[L2 cache]], which was very easy to manufacture, cheap, and simple to enlarge to any desired size (typical cache sizes were 512&nbsp;KB or 1&nbsp;MB), but they carried the performance penalty of slower cache performance, typically running at a [[Front-side bus|FSB]] frequency of 60 to 100&nbsp;MHz. The Pentium II's 512&nbsp;KB of L2 cache was implemented with a pair of relatively high-performance L2 cache chips mounted on a special-purpose board alongside the processor itself, running at half the processor's clock rate and communicating with the CPU through a special [[back-side bus]]. This method of cache placement was expensive and imposed practical cache-size limits, but allowed the Pentium II to be clocked higher and avoided front side bus RAM/L2 cache contention typical with motherboard-placed L2 cache configurations.<ref>{{cite news|last=Joch |first=Alan |title=Buses: Front-side and backside |url=http://www.itworld.com/Comp/1091/CWD010430STO60015/ |publisher=ITworld.com |date=April 30, 2001 |access-date=July 30, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20010502134148/http://www.itworld.com/Comp/1091/CWD010430STO60015/ |archive-date=May 2, 2001 |df=dmy }}</ref>

Over time, newer Mendocino processors were released at 333, 366, 400, 433, 466, 500, and 533&nbsp;MHz. The Mendocino Celeron CPU came only designed for a 66&nbsp;MHz front-side bus, but this would not be a serious performance bottleneck until clock rates reached higher levels.

The Mendocino Celerons also introduced new packaging. When the Mendocinos debuted they came in both a Slot 1 SEPP and [[Socket 370]] [[Pin grid array#Plastic|PPGA]] package. The Slot 1 form had been designed to accommodate the off-chip cache of the Pentium II and had mounting problems with motherboards. Because all Celerons are a single-chip design, however, there was no reason to retain the slot packaging for L2 cache storage, and Intel discontinued the Slot 1 variant; beginning with the 466&nbsp;MHz part, only the PPGA Socket 370 form was offered. (Third-party manufacturers made motherboard slot-to-socket adapters (nicknamed [[Slotket]]s) available for a few dollars, which allowed, for example, a Celeron 500 to be fitted to a Slot 1 motherboard.) One interesting note about the PPGA Socket 370 Mendocinos is they supported [[symmetric multiprocessing]] (SMP), and there was at least one motherboard released (the [[ABIT BP6]]) which took advantage of this fact.

The Mendocino also came in a mobile variant, with clock rates of 266, 300, 333, 366, 400, 433 and 466&nbsp;MHz.

In Intel's "Family/Model/Stepping" scheme, Mendocino CPUs are family 6, model 6 and their Intel product code is 80524. These identifiers are shared with the related ''Dixon'' Mobile Pentium II variant.