Editing Classic RISC pipeline (section)

===Memory access===

If data memory needs to be accessed, it is done in this stage.

During this stage, single cycle latency instructions simply have their results forwarded to the next stage. This forwarding ensures that both one and two cycle instructions always write their results in the same stage of the pipeline so that just one write port to the register file can be used, and it is always available.

For direct mapped and virtually tagged data caching, the simplest by far of the [[CPU cache|numerous data cache organizations]], two [[Static RAM|SRAMs]] are used, one storing data and the other storing tags.