Editing Cray-3 (section)

===Logical design===
The Cray-3 system architecture comprised a ''foreground processing system'', up to 16 ''background processors'' and up to 2 gigawords (16 GB) of ''common memory''. The foreground system was dedicated to [[input/output]] and system management. It included a 32-bit processor and four synchronous data channels for [[mass storage]] and network devices, primarily via [[HiPPI]] channels.{{sfn|Brochure|1993|p=6}}

Each background processor consisted of a ''computation section'', a ''control section'' and ''local memory''. The computation section performed [[64-bit]] scalar, [[floating point]] and [[Vector processor|vector arithmetic]]. The control section provided instruction buffers, memory management functions, and a [[real-time clock]]. 16 kilowords (128 kbytes) of high-speed local memory was incorporated into each background processor for use as temporary scratch memory.{{sfn|Brochure|1993|p=4}}

Common memory consisted of silicon [[CMOS]] [[Static Random Access Memory|SRAM]], organized into ''octants'' of 64 banks each, with up to eight octants possible. The [[word size]] was 64-bits plus eight [[error-correction]] bits, and total memory bandwidth was rated at 128 gigabytes per second.{{sfn|Brochure|1993|p=5}}