Editing Dual in-line package (section)

==Construction==
[[File:DIP Cross-section.svg|thumb|upright=0.8|Side view of a dual in-line package (DIP) IC]]
[[File:DIP zagotovka.jpg|thumb|Dual in-line (DIP) integrated circuit metal tape base with contacts]]
The body (housing) of a DIP containing an IC chip is usually made from molded plastic or ceramic. The hermetic nature of a ceramic housing is preferred for extremely high reliability devices. However, the vast majority of DIPs are manufactured via a thermoset molding process in which an epoxy mold compound is heated and transferred under pressure to encapsulate the device. Typical cure cycles for the resins are less than 2 minutes and a single cycle may produce hundreds of devices.

The leads emerge from the longer sides of the package along the seam, parallel to the top and bottom planes of the package, and are bent downward approximately 90 degrees (or slightly less, leaving them angled slightly outward from the centerline of the package body). (The [[Small-outline integrated circuit|SOIC]], the SMT package that most resembles a typical DIP, appears essentially the same, notwithstanding size scale, except that after being bent down the leads are bent upward again by an equal angle to become parallel with the bottom plane of the package.) In ceramic (CERDIP) packages, an epoxy or grout is used to hermetically seal the two halves together, providing an [[air]] and [[moisture]] tight seal to protect the IC [[Die (integrated circuit)|die]] inside. Plastic DIP (PDIP) packages are usually sealed by fusing or cementing the plastic halves around the leads, but a high degree of [[hermeticity]] is not achieved because the plastic itself is usually somewhat porous to moisture and the process cannot ensure a good microscopic seal between the leads and the plastic at all points around the perimeter. However, contaminants are usually still kept out well enough that the device can operate reliably for decades with reasonable care in a controlled environment.

Inside the package, the lower half has the leads embedded, and at the center of the package is a rectangular space, chamber, or void into which the IC die is cemented. The leads of the package extend diagonally inside the package from their positions of emergence along the periphery to points along a rectangular perimeter surrounding the die, tapering as they go to become fine contacts at the die. Ultra-fine [[bond wire]]s (barely visible to the naked human eye) are welded between these die periphery contacts and bond pads on the die itself, connecting one lead to each bond pad, and making the final connection between the microcircuits and the external DIP leads. The bond wires are not usually taut but loop upward slightly to allow slack for thermal expansion and contraction of the materials; if a single bond wire breaks or detaches, the entire IC may become useless. The top of the package covers all of this delicate assemblage without crushing the bond wires, protecting it from contamination by foreign materials.

Usually, a company logo, alphanumeric codes and sometimes words are printed on top of the package to identify its manufacturer and type, when it was made (usually as a year and a week number), sometimes where it was made, and other proprietary information (perhaps revision numbers, manufacturing plant codes, or stepping ID codes.)

The necessity of laying out all of the leads in a basically radial pattern in a single plane from the die perimeter to two rows on the periphery of the package is the main reason that DIP packages with higher lead counts must have wider spacing between the lead rows, and it effectively limits the number of leads which a practical DIP package may have. Even for a very small die with many bond pads (e.g. a chip with 15 inverters, requiring 32 leads), a wider DIP would still be required to accommodate the radiating leads internally. This is one of the reasons that four-sided and multiple rowed packages, such as [[Pin grid array|PGAs]], were introduced (around the early 1980s).

A large DIP package (such as the DIP64 used for the [[Motorola 68000]] CPU) has long leads inside the package between pins and the die, making such a package unsuitable for high speed devices.

Some other types of DIP devices are built very differently. Most of these have molded plastic housings and straight leads or leads that extend directly out of the bottom of the package. For some, LED displays particularly, the housing is usually a hollow plastic box with the bottom/back open, filled (around the contained electronic components) with a hard translucent epoxy material from which the leads emerge. Others, such as DIP switches, are composed of two (or more) plastic housing parts snapped, welded, or glued together around a set of contacts and tiny mechanical parts, with the leads emerging through molded-in holes or notches in the plastic.

===Variants===
[[Image:Nec8080.png|thumb|upright=1.4|Several PDIPs and CERDIPs. The large CERDIP in the foreground is an NEC 8080AF ([[Intel 8080]]-compatible) microprocessor.]]

Several DIP variants for ICs exist, mostly distinguished by packaging material:
* '''Ceramic dual in-line package (CERDIP or CDIP)'''
* '''Plastic dual in-line package (PDIP)'''
* '''Shrink plastic dual in-line package (SPDIP)''' &ndash; A denser version of the PDIP with a 0.07 in (1.778&nbsp;mm) lead pitch.
* '''Skinny dual in-line package (SDIP or SPDIP<ref>For instance, Microchip: http://www.microchip.com/packaging</ref>)''' &ndash; Sometimes used to refer to a "narrow" 0.300 in. (or 300 [[Thousandth of an inch|mil]]) wide DIP, normally when clarification is needed e.g. for DIP with 24 pins or more, which usually come in "wide" 0.600&nbsp;in wide DIP package. An example of a typical proper full spec for a "narrow" DIP package would be 300&nbsp;mil body width, {{convert|0.1|in|mm|2}} pin pitch.

[[EPROM]]s were sold in ceramic DIPs manufactured with a circular window of clear quartz over the chip die to allow the part to be erased by [[ultraviolet light]]. Often, the same chips were also sold in less expensive windowless PDIP or CERDIP packages as [[EPROM#Details|one-time programmable]] (OTP) versions. Windowed and windowless packages were also used for microcontrollers, and other devices, containing EPROM memory. Windowed CERDIP-packaged EPROMs were used for the [[BIOS]] ROM of many early IBM PC clones with an adhesive label covering the window to prevent inadvertent erasure through exposure to ambient light.

Molded plastic DIPs are much lower in cost than ceramic packages; one 1979 study showed that a plastic 14 pin DIP cost around US$0.063 and a ceramic package cost US$0.82.<ref>Rao R. Tummala, Eugene J. Rymaszewski, Alan G. Klopfenstein ''Microelectronics Packaging Handbook: Semiconductor packaging'', Springer, 1997 {{ISBN|0-412-08441-4}} page 395</ref>

===Single in-line===
{{distinguish|SIPP memory}}
[[Image:SIL9 ST TDA4601.jpg|thumb|upright=1|Package sample for single in-line package (SIP or SIL) devices]]

A '''single in-line package''' ('''SIP''' or '''SIL package''')<ref>{{cite web |title=Single-in-Line Package (SIP) |url=https://eesemi.com/sip-package.htm |website=EE Semi |archive-url=https://web.archive.org/web/20210818201818/https://eesemi.com/sip-package.htm |archive-date=August 18, 2021 |url-status=live}}</ref> has one row of connecting pins. It is not as popular as the DIP, but has been used for packaging [[RAM]] chips and multiple resistors with a common pin. As compared to DIPs with a typical maximum pin count of 64, SIPs have a typical maximum pin count of 24 with lower package costs.<ref>Pecht, M. (1994). [https://books.google.com/books?id=hDwX3slSvQ4C&dq=advantages+disadvantages+single+inline+package&pg=PA48 Integrated circuit, hybrid, and multichip module package design guidelines]. Wiley-IEEE.</ref>

One variant of the single in-line package uses part of the lead frame for a heat sink tab. This [[multi-leaded power package]] is useful for such applications as audio power amplifiers, for example.

===Quad in-line===
[[File:R6511.jpg|thumb|upright=1|A Rockwell [[6502]]-based microcontroller in a QIP]]
{{Main|Quad in-line package}}

The QIP, sometimes called a ''QIL package'', has the same dimensions as a DIL package, but the leads on each side are bent into an alternating zigzag configuration so as to fit four lines of solder pads (instead of two with a DIL). The QIL design increased the spacing between solder pads without increasing package size, for two reasons: 	
# It allowed more reliable [[soldering]]. This may seem odd today, given the far closer solder pad spacing in use now, but in the 1970s, the heyday of the QIL, [[solder bridge|bridging]] of neighbouring solder pads on DIL chips was an issue at times,
# QIL also increased the possibility of running a [[copper]] track between 2 solder pads. This was very handy on the then standard single sided single layer PCBs.

===Lead count and spacing===
Commonly found DIP packages that conform to [[JEDEC]] standards use an inter-lead spacing (lead pitch) of {{convert|0.1|in|mm|2}} (JEDEC MS-001BA). Row spacing varies depending on lead counts, with 0.3 in. (7.62&nbsp;mm) (JEDEC MS-001) or 0.6&nbsp;inch (15.24&nbsp;mm) (JEDEC MS-011) the most common. Less common standardized row spacings include 0.4&nbsp;inch (10.16&nbsp;mm) (JEDEC MS-010) and 0.9&nbsp;inch (22.86&nbsp;mm), as well as a row spacing of 0.3&nbsp;inch, 0.6&nbsp;inch or 0.75&nbsp;inch with a 0.07&nbsp;inch (1.778&nbsp;mm) lead pitch.

The former Soviet Union and Eastern bloc countries used similar packages, but with a metric pin-to-pin spacing of 2.5&nbsp;mm rather than {{convert|0.1|in|mm|2}}.

The number of leads is always even. For 0.3&nbsp;inch spacing, typical lead counts are 8, 14, 16, and 20; less common are 4, 6, 18, 24, and 28 lead counts. To have an even number of leads {{anchor|NC}}some DIPs have unused [[not connected]] (NC)<ref group="nb" name="NB_NC"/> leads to the internal chip, or are duplicated, e.g. two ground pins. For 0.6&nbsp;inch spacing, typical lead counts are 24, 28, 32, and 40; less common are 36, 42, 48, 52, and 64 lead counts. Some microprocessors, such as the [[Motorola 68000]] and [[Zilog Z180]], used lead counts as high as 64; this is typically the maximum number of leads for a DIP package.<ref name="CMOS_DI">{{cite book |title=CMOS digital integrated circuits |last=Kang |first=Sung-Mo |author2=Leblebici, Yusuf |year=2002 |publisher=McGraw-Hill |isbn=0-07-246053-9 |page=42|edition=3rd }}</ref>