Editing Dynamic random-access memory (section)

===Operations to read a data bit from a DRAM storage cell===
# The sense amplifiers are disconnected.<ref name="Kenner:24,30">{{harvnb|Keeth|Baker|Johnson|Lin|2007|pp=24–30}}</ref>
# The bit-lines are precharged to exactly equal voltages that are in between high and low logic levels (e.g., 0.5&nbsp;V if the two levels are 0 and 1&nbsp;V). The bit-lines are physically symmetrical to keep the capacitance equal, and therefore at this time their voltages are equal.<ref name="Kenner:24,30"/>
# The precharge circuit is switched off. Because the bit-lines are relatively long, they have enough [[capacitance]] to maintain the precharged voltage for a brief time. This is an example of [[dynamic logic (digital logic)|dynamic logic]].<ref name="Kenner:24,30"/>
# The desired row's word-line is then driven high to connect a cell's storage capacitor to its bit-line. This causes the transistor to conduct, transferring [[Electric charge|charge]] from the storage cell to the connected bit-line (if the stored value is 1) or from the connected bit-line to the storage cell (if the stored value is 0). Since the capacitance of the bit-line is typically much higher than the capacitance of the storage cell, the voltage on the bit-line increases very slightly if the storage cell's capacitor is discharged and decreases very slightly if the storage cell is charged (e.g., 0.54 and 0.45&nbsp;V in the two cases). As the other bit-line holds 0.50&nbsp;V there is a small voltage difference between the two twisted bit-lines.<ref name="Kenner:24,30"/>
# The sense amplifiers are now connected to the bit-lines pairs. Positive feedback then occurs from the cross-connected inverters, thereby amplifying the small voltage difference between the odd and even row bit-lines of a particular column until one bit line is fully at the lowest voltage and the other is at the maximum high voltage. Once this has happened, the row is ''open'' (the desired cell data is available).<ref name="Kenner:24,30"/>
# All storage cells in the open row are sensed simultaneously, and the sense amplifier outputs latched. A column address then selects which latch bit to connect to the external data bus. Reads of different columns in the same row can be performed without a [[Memory timings|row opening delay]] because, for the open row, all data has already been sensed and latched.<ref name="Kenner:24,30"/>
# While reading of columns in an open row is occurring, current is flowing back up the bit-lines from the output of the sense amplifiers and recharging the storage cells. This reinforces (i.e. refreshes) the charge in the storage cell by increasing the voltage in the storage capacitor if it was charged to begin with, or by keeping it discharged if it was empty.  Note that due to the length of the bit-lines there is a fairly long propagation delay for the charge to be transferred back to the cell's capacitor. This takes significant time past the end of sense amplification, and thus overlaps with one or more column reads.<ref name="Kenner:24,30"/>
# When done with reading all the columns in the current open row, the word-line is switched off to disconnect the storage cell capacitors (the row is closed) from the bit-lines. The sense amplifier is switched off, and the bit-lines are precharged again.<ref name="Kenner:24,30"/>