Editing Electronic design automation (section)

== Software focuses ==
{{technical|date=February 2017}}

=== Design ===
[[Image:Kicad Eeschema screenshot.jpg|thumb|right|380px|Schematic capture program]]
{{Main|Design flow (EDA)}}Design flow primarily remains characterised via several primary components; these include:
* [[High-level synthesis]] (additionally known as behavioral synthesis or algorithmic synthesis) &ndash; The high-level design description (e.g. in C/C++) is converted into [[Register-transfer level|RTL]] or the register transfer level, responsible for representing circuitry via the utilisation of interactions between registers.
*[[Logic synthesis]] &ndash; The translation of [[Register-transfer level|RTL]] design description (e.g. written in Verilog or VHDL) into a discrete [[netlist]] or representation of logic gates.
*[[Schematic capture]] &ndash; For standard cell digital, analog, RF-like Capture CIS in Orcad by Cadence and ISIS in Proteus.{{clarify|date=September 2020}}
*[[Placement (EDA)|Layout]] &ndash; usually [[schematic-driven layout]], like Layout in Orcad by Cadence, ARES in Proteus

=== Simulation ===
{{Main|Electronic circuit simulation}}
[[File:Eda-fabrication.PNG|right|thumb|250px|Simulated lithographic and other fabrication defects visible in small standard-cell metal interconnects.]]
* [[SPICE|Transistor simulation]] – low-level transistor-simulation of a schematic/layout's behavior, accurate at device-level.
* [[Logic simulation]] – digital-simulation of an [[Register-transfer level|RTL]] or gate-netlist's digital ([[Boolean algebra|Boolean]] 0/1) behavior, accurate at Boolean-level.
* Behavioral simulation – high-level simulation of a design's architectural operation, accurate at cycle-level or interface-level.
* [[Hardware emulation]] – Use of special purpose hardware to emulate the logic of a proposed design. Can sometimes be plugged into a system in place of a yet-to-be-built chip; this is called '''[[in-circuit emulation]]'''.
* [[Technology CAD]] simulate and analyze the underlying process technology. Electrical properties of devices are derived directly from device physics

=== Analysis and verification ===
* [[Functional verification]]: ensures [[Circuit (computer science)|logic design]] matches specifications and executes tasks correctly. Includes dynamic functional verification via simulation, emulation, and prototypes.<ref>{{Cite web |date=March 17, 2017 |title=Functional Verification |url=https://semiengineering.com/knowledge_centers/eda-design/verification/functional-verification/ |access-date=April 10, 2023 |website=Semiconductor Engineering}}</ref>
* RTL Linting for adherence to coding rules such as syntax, semantics, and style.<ref>BTV [https://besttechviews.com/rtl-linting-tools-reviews-metrics/ RTL Linting.] Retrieved January 2, 2023</ref>
*[[Clock domain crossing|Clock domain crossing verification]] (CDC check): similar to [[Lint programming tool|linting]], but these checks/tools specialize in detecting and reporting potential issues like [[data loss]], [[Metastability in electronics|meta-stability]] due to use of multiple [[clock domain]]s in the design.
* [[Formal verification]], also [[model checking]]: attempts to prove, by mathematical methods, that the system has certain desired properties, and that some undesired effects (such as [[deadlock (computer science)|deadlock]]) cannot occur.
* [[Formal equivalence checking|Equivalence checking]]: algorithmic comparison between a chip's RTL-description and synthesized gate-[[netlist]], to ensure functional equivalence at the ''logical'' level.
* [[Static timing analysis]]: analysis of the timing of a circuit in an input-independent manner, hence finding a worst case over all possible inputs.
* [[Layout extraction]]: starting with a proposed layout, compute the (approximate) electrical characteristics of every wire and device.  Often used in conjunction with static timing analysis above to estimate the performance of the completed chip.
* [[Electromagnetic field solver]]s, or just [[Electromagnetic field solver|field solvers]], solve Maxwell's equations directly for cases of interest in IC and PCB design. They are known for being slower but more accurate than the [[layout extraction]] above.
* [[Physical verification]], PV: checking if a design is physically manufacturable, and that the resulting chips will not have any function-preventing physical defects, and will meet original specifications.

=== Manufacturing preparation ===
* [[Mask data preparation]] or MDP - The generation of actual [[Photolithography|lithography]] [[photomask]]s, utilised to physically manufacture the chip.
** ''Chip finishing'' which includes custom designations and structures to improve [[design for manufacturability (IC)|manufacturability]] of the layout. Examples of the latter are a seal ring and filler structures.<ref name="Layout">{{cite book|author=J. Lienig, J. Scheible|title=Fundamentals of Layout Design for Electronic Circuits|url=https://link.springer.com/book/10.1007/978-3-030-39284-0|pages=102–110|chapter=Chap. 3.3: Mask Data: Layout Post Processing|publisher=Springer|date=2020|doi=10.1007/978-3-030-39284-0|isbn=978-3-030-39284-0|s2cid=215840278}}</ref> 
** Producing a ''reticle layout'' with test patterns and alignment marks. 
**''Layout-to-mask preparation'' that enhances layout data with graphics operations, such as [[resolution enhancement techniques]] (RET) – methods for increasing the quality of the final [[photomask]]. This also includes [[optical proximity correction]]  (OPC) or [[inverse lithography technology]] (ILT)  – the up-front compensation for [[diffraction]] and [[Interference (wave propagation)|interference]] effects occurring later when chip is manufactured using this mask.
** ''[[Mask generation]]'' – The generation of flat mask image from hierarchical design.
** ''[[Automatic test pattern generation]]'' or ATPG – The generation of pattern data systematically to exercise as many logic-gates and other components as possible.
** ''[[Built-in self-test]]'' or BIST – The installation of self-contained test-controllers to automatically test a logic or memory structure in the design

=== Functional safety ===
* [[Functional safety]] analysis, systematic computation of [[Failures In Time|failure in time]] (FIT) rates and diagnostic coverage metrics for designs in order to meet the compliance requirements for the desired safety integrity levels.
* Functional safety synthesis, add reliability enhancements to structured elements (modules, RAMs, ROMs, register files, FIFOs) to improve fault detection / fault tolerance. This includes (not limited to) addition of error detection and / or correction codes (Hamming), redundant logic for fault detection and fault tolerance (duplicate / triplicate) and protocol checks (interface parity, address alignment, beat count)
* Functional safety verification, running of a fault campaign, including insertion of faults into the design and verification that the safety mechanism reacts in an appropriate manner for the faults that are deemed covered.
[[Image:Gschem and gerbv.jpg|thumb|right|380px|PCB layout and schematic for connector design]]