Editing Flash memory (section)

====Charge trap flash====
{{Main|Charge trap flash}}

[[Charge trap flash]] (CTF) technology replaces the polysilicon floating gate, which is sandwiched between a blocking gate oxide above and a tunneling oxide below it, with an electrically insulating silicon nitride layer; the silicon nitride layer traps electrons. In theory, CTF is less prone to electron leakage, providing improved data retention.<ref name="electronicdesign-20130415">{{Cite news |last=Wong |first=Bill |date=15 April 2013 |title=Interview: Spansion's CTO Talks About Embedded Charge Trap NOR Flash Technology |work=Electronic Design |url=https://www.electronicdesign.com/technologies/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |url-status=live |archive-url=https://web.archive.org/web/20231204125719/https://www.electronicdesign.com/technologies/embedded/digital-ics/memory/article/21796009/interview-spansions-cto-talks-about-embedded-charge-trap-nor-flash-technology |archive-date=4 December 2023 }}</ref><ref name="ito-taito-2017">{{Cite book |last1=Ito |first1=Takashi |title=Embedded Flash Memory for Embedded Systems: Technology, Design for Sub-systems, and Innovations  |last2=Taito |first2=Yasuhiko |date=9 September 2017 |publisher=[[Springer Publishing]] |isbn=978-3-319-55306-1 |editor-last=Hidaka |editor-first=Hideto |series=Integrated Circuits and Systems |pages=209–244 |chapter=SONOS Split-Gate eFlash Memory |doi=10.1007/978-3-319-55306-1_7 }}</ref><ref name="ieee-91-4">{{Cite journal |last1=Bez |first1=Roberto |last2=Camerlenghi |first2=E. |last3=Modelli |first3=Alberto |last4=Visconti |first4=Angelo |date=April 2003 |title=Introduction to flash memory |journal=[[Proceedings of the IEEE]] |publisher=[[Institute of Electrical and Electronics Engineers]] |volume=91 |issue=4 |pages=498–502 |doi=10.1109/JPROC.2003.811702 }}</ref><ref name="lee-2011">{{Cite journal |last=Lee |first=Jang-Sik |date=18 October 2011 |title=Review paper: Nano-floating gate memory devices |journal=Electronic Materials Letters |publisher=Korean Institute of Metals and Materials |volume=7 |issue=3 |pages=175–183 |doi=10.1007/s13391-011-0901-5 |bibcode=2011EML.....7..175L |s2cid=110503864 }}</ref><ref name="auto5">{{Cite web |last=Aravindan |first=Avinash |date=13 November 2018 |title=Flash 101: Types of NAND Flash |url=https://www.embedded.com/flash-101-types-of-nand-flash/ |url-status=live |archive-url=https://web.archive.org/web/20231106101540/https://www.embedded.com/flash-101-types-of-nand-flash/ |archive-date=6 November 2023 |website=embedded.com }}</ref><ref name="nanoscale-9-1-526">{{Cite journal |last1=Meena |first1=Jagan Singh |last2=Sze |first2=Simon Min |last3=Chand |first3=Umesh |last4=Tseng |first4=Tseung-Yuen |date=25 September 2014 |title=Overview of emerging nonvolatile memory technologies |journal=Nanoscale Research Letters |volume=9 |issue=1 |page=526 |doi=10.1186/1556-276x-9-526 |issn=1556-276X |id=526 |doi-access=free |pmid=25278820 |pmc=4182445 |bibcode=2014NRL.....9..526M }}</ref>

Because CTF replaces the polysilicon with an electrically insulating nitride, it allows for smaller cells and higher endurance (lower degradation or wear). However, electrons can become trapped and accumulate in the nitride, leading to degradation. Leakage is exacerbated at high temperatures since electrons become more excited with increasing temperatures. CTF technology, however, still uses a tunneling oxide and blocking layer, which are the weak points of the technology, since they can still be damaged in the usual ways (the tunnel oxide can be degraded due to extremely high electric fields and the blocking layer due to Anode Hot Hole Injection (AHHI).<ref name="techtarget-20230619">{{Cite web |last=Sheldon |first=Robert |date=19 June 2023 |title=Charge trap technology advantages for 3D NAND flash drives |url=https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |url-status=live |archive-url=https://web.archive.org/web/20230809223937/https://www.techtarget.com/searchstorage/tip/Charge-trap-technology-advantages-for-3D-NAND-flash-drives |archive-date=9 August 2023 |website=SearchStorage }}</ref><ref name="grossi-zambelli-olivo-2016">{{Cite book |last1=Grossi |first1=A. |title=3D Flash Memories |last2=Zambelli |first2=C. |last3=Olivo |first3=P. |date=7 June 2016 |publisher=[[Springer Science+Business Media]] |isbn=978-94-017-7512-0 |editor-last=Micheloni |editor-first=Rino |location=Dordrecht |pages=29–62 |chapter=Reliability of 3D NAND Flash Memories |doi=10.1007/978-94-017-7512-0_2 }}</ref>

Degradation or wear of the oxides is the reason why flash memory has limited endurance. Data retention goes down (the potential for data loss increases) with increasing degradation, since the oxides lose their electrically-insulating characteristics as they degrade. The oxides must insulate against electrons to prevent them from leaking, which would cause data loss.

In 1991, [[NEC]] researchers, including N. Kodama, K. Oyama and Hiroki Shirai, described a type of flash memory with a charge-trap method.<ref name="iedm-1991-symmetrical">{{Cite conference |last1=Kodama |first1=N. |last2=Oyama |first2=K. |last3=Shirai |first3=H. |last4=Saitoh |first4=K. |last5=Okazawa |first5=T. |last6=Hokari |first6=Y. |date=December 1991 |title=A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory |conference=[[International Electron Devices Meeting]] |location=Washington, DC  |publisher=[[Institute of Electrical and Electronics Engineers|IEEE]] |pages=303–306 |doi=10.1109/IEDM.1991.235443 |isbn=0-7803-0243-5 |issn=0163-1918 |s2cid=111203629 }}</ref> In 1998, Boaz Eitan of [[Saifun Semiconductors]] (later acquired by [[Spansion]]) [[patented]] a flash memory technology named NROM that took advantage of a charge trapping layer to replace the conventional [[floating gate]] used in conventional flash memory designs.<ref>{{cite web|last=Eitan|first=Boaz|title=US Patent 5,768,192: Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping|url=http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5,768,192.PN.&OS=PN/5,768,192&RS=PN/5,768,192|publisher=US Patent & Trademark Office|access-date=22 May 2012|archive-date=22 February 2020|archive-url=https://web.archive.org/web/20200222215754/http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=5%2C768%2C192.PN.&OS=PN%2F5%2C768%2C192&RS=PN%2F5%2C768%2C192|url-status=dead}}</ref> In 2000, an [[Advanced Micro Devices]] (AMD) research team led by Richard M. Fastow, Egyptian engineer Khaled Z. Ahmed and Jordanian engineer Sameer Haddad (who later joined Spansion) demonstrated a charge-trapping mechanism for NOR flash memory cells.<ref name="ieee-letters-21-4">{{Cite journal |last1=Fastow |first1=Richard M. |last2=Ahmed |first2=Khaled Z. |last3=Haddad |first3=Sameer |last4=Randolph |first4=Mark |last5=Huster |first5=C. |last6=Hom |first6=P. |date=April 2000 |title=Bake induced charge gain in NOR flash cells |url=https://www.researchgate.net/publication/3253902 |journal=[[IEEE Electron Device Letters]] |volume=21 |issue=4 |pages=184–186 |bibcode=2000IEDL...21..184F |doi=10.1109/55.830976 |issn=1558-0563 |s2cid=24724751 }}</ref> CTF was later commercialized by AMD and [[Fujitsu]] in 2002.<ref name="auto3">{{Cite news |last=Hruska |first=Joel |date=6 August 2013 |title=Samsung produces first 3D NAND, aims to boost densities, drive lower cost per GB |work=[[ExtremeTech]] |url=https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |url-status=live |access-date=4 July 2019 |archive-url=https://web.archive.org/web/20231102133725/https://www.extremetech.com/computing/163221-samsung-produces-first-3d-nand-aims-to-boost-densities-drive-lower-cost-per-gb |archive-date=2 November 2023 }}</ref> 3D [[V-NAND]] (vertical NAND) technology stacks NAND flash memory cells vertically within a chip using 3D charge trap flash (CTP) technology. 3D V-NAND technology was first announced by Toshiba in 2007,<ref name="toshiba-3d"/> and the first device, with 24 layers, was commercialized by [[Samsung Electronics]] in 2013.<ref name="samsung-3d"/><ref name="samsung-3d-ee"/>