Editing Hamming weight (section)

== Processor support ==
* The [[IBM STRETCH]] computer in the 1960s calculated the number of set bits as well as the [[number of leading zeros]] as a by-product of all logical operations.<ref name="Warren_2013"/>
* [[Cray]] supercomputers early on featured a population count [[machine instruction]], rumoured to have been specifically requested by the U.S. government [[National Security Agency]] for [[cryptanalysis]] applications.<ref name="Warren_2013"/><!-- This ref supports the rumour in general, but does not mention Cray -->
* [[Control Data Corporation]]'s (CDC) [[CDC 6000 series|6000]] and [[CDC Cyber|Cyber 70/170]] series machines included a population count instruction; in [[COMPASS#COMPASS for 60-bit machines|COMPASS]], this instruction was coded as <code>CXi</code>.
* The 64-bit [[SPARC]] version 9 architecture defines a <code>POPC</code> instruction,<ref name="SPARC_1992"/><ref name="Warren_2013"/> but most implementations do not implement it, requiring it be emulated by the operating system.<ref name="JDK_BitCount"/>
* [[Donald Knuth]]'s model computer [[MMIX]] that is going to replace [[MIX (abstract machine)|MIX]] in his book [[The Art of Computer Programming]] has an <code>SADD</code> instruction since 1999. <code>SADD a,b,c</code> counts all bits that are 1 in b and 0 in c and writes the result to a.
* [[Compaq]]'s [[Alpha 21264A]], released in 1999, was the first Alpha series CPU design that had the count extension (<code>CIX</code>).
* [[Analog Devices]]' [[Blackfin]] processors feature the <code>ONES</code> instruction to perform a 32-bit population count.<ref name="AD_2001"/>
* [[AMD]]'s [[AMD K10|Barcelona]] architecture introduced the advanced bit manipulation (ABM) [[Instruction set|ISA]] introducing the <code>POPCNT</code> instruction as part of the [[SSE4a]] extensions in 2007.
* [[Intel Core]] processors introduced a <code>POPCNT</code> instruction with the [[SSE4.2]] [[instruction set]] extension, first available in a [[Nehalem (microarchitecture)|Nehalem]]-based [[Core i7]] processor, released in November 2008.
* The [[ARM architecture]] introduced the <code>VCNT</code> instruction as part of the [[ARM Advanced SIMD|Advanced SIMD]] ([[NEON (instruction set)|NEON]]) extensions.
* The [[RISC-V]] architecture introduced the <code>CPOP</code> instruction as part of the Bit Manipulation (B) extension.<ref name="RISC-V-B"/>