Editing HyperTransport (section)

== Applications ==
=== Front-side bus replacement ===
The primary use for HyperTransport is to replace the Intel-defined [[front-side bus]], which is different for every type of Intel processor.  For instance, a [[Pentium compatible processor|Pentium]] cannot be plugged into a [[PCI Express]] bus directly, but must first go through an adapter to expand the system. The proprietary front-side bus must connect through adapters for the various standard buses, like [[Accelerated Graphics Port|AGP]] or PCI Express. These are typically included in the respective controller functions, namely the ''[[Northbridge (computing)|northbridge]]'' and ''[[Southbridge (computing)|southbridge]]''.

In contrast, HyperTransport is an open specification, published by a multi-company consortium. A single HyperTransport adapter chip will work with a wide spectrum of HyperTransport enabled microprocessors.

[[AMD]] used HyperTransport to replace the [[front-side bus]] <!-- There was a reason the article was titled "Front side bus" (now Front-side bus): it is correct.  Just because some phrase has an acronym does not mean its constituent words should be capitalized. --> in their [[Opteron]], [[Athlon 64]], [[Athlon II]], [[Sempron 64]], [[Turion 64]], [[Phenom (processor)|Phenom]], [[Phenom II]] and [[Bulldozer (microarchitecture)|FX]] families of microprocessors.

=== Multiprocessor interconnect ===
Another use for HyperTransport is as an interconnect for [[Non-Uniform Memory Access|NUMA]] [[multiprocessor]] computers. AMD used HyperTransport with a proprietary [[cache coherency]] extension as part of their Direct Connect Architecture in their [[Opteron]] and [[Athlon 64 FX]] ([[AMD Quad FX platform|Dual Socket Direct Connect (DSDC) Architecture]]) line of processors. [[#Infinity Fabric|Infinity Fabric]] used with the [[EPYC]] server CPUs is a superset of HyperTransport. The [[HORUS interconnect]] from [[Newisys]] extends this concept to larger clusters. The Aqua device from 3Leaf Systems virtualizes and interconnects CPUs, memory, and I/O.

=== Router or switch bus replacement ===
HyperTransport can also be used as a bus in [[Router (computing)|router]]s and [[Network switch|switches]]. Routers and switches have multiple network interfaces, and must forward data between these ports as fast as possible. For example, a four-port, 1000&nbsp;[[Mbit]]/s [[Ethernet]] router needs a maximum 8000&nbsp;Mbit/s of internal bandwidth (1000&nbsp;Mbit/s × 4 ports × 2 directions)—HyperTransport greatly exceeds the bandwidth this application requires. However a 4 + 1 port 10&nbsp;Gb router would require 100&nbsp;Gbit/s of internal bandwidth. Add to that 802.11ac 8 antennas and the WiGig 60&nbsp;GHz standard (802.11ad) and HyperTransport becomes more feasible (with anywhere between 20 and 24 lanes used for the needed bandwidth).

=== Co-processor interconnect ===
The issue of latency and bandwidth between CPUs and co-processors has usually been the major stumbling block to their practical implementation. Co-processors such as [[FPGAs]] have appeared that can access the HyperTransport bus and become integrated on the motherboard. Current generation FPGAs from both main manufacturers ([[Altera]] and [[Xilinx]]) directly support the HyperTransport interface, and have [[Semiconductor intellectual property core|IP Cores]] available.  Companies such as XtremeData, Inc. and DRC take these FPGAs (Xilinx in DRC's case) and create a module that allows FPGAs to plug directly into the Opteron socket.

AMD started an initiative named [[Torrenza]] on September 21, 2006, to further promote the usage of HyperTransport for plug-in cards and [[coprocessors]].  This initiative opened their "Socket F" to plug-in boards such as those from XtremeData and DRC.

=== Add-on card connector (HTX and HTX3) ===
[[File:HyperTransport16 pcie8riser pcie16.jpg|thumb|Connectors from top to bottom: HTX, PCI-Express for riser card, PCI-Express]]
A connector specification that allows a slot-based peripheral to have direct connection to a microprocessor using a HyperTransport interface was released by the HyperTransport Consortium.  It is known as '''H'''yper'''T'''ransport e'''X'''pansion ('''HTX''').  Using a reversed instance of the same mechanical connector as a 16-lane [[PCI Express]] slot (plus an x1 connector for power pins), HTX allows development of plug-in cards that support direct access to a CPU and [[Direct memory access|DMA]] to the system [[RAM]]. The initial card for this slot was the [[QLogic]] InfiniPath InfiniBand HCA. IBM and [[Hewlett-Packard|HP]], among others, have released HTX compliant systems.

The original HTX standard is limited to 16{{nbsp}}bits and 800{{nbsp}}MHz.<ref>{{cite web |last1=Emberson |first1=David |last2=Holden |first2=Brian |date=December 12, 2007 |title=HTX specification |url=http://www.hypertransport.org/docs/uploads/HTX_Specifications.pdf |website=HyperTransport Consortium |page=4 |access-date=January 30, 2008 |url-status=dead |archive-url=https://web.archive.org/web/20120308085021/http://www.hypertransport.org/docs/uploads/HTX_Specifications.pdf |archive-date=March 8, 2012}}</ref>

In August 2008, the HyperTransport Consortium released HTX3, which extends the clock rate of HTX to 2.6&nbsp;GHz (5.2&nbsp;GT/s, 10.7&nbsp;GTi, 5.2 real GHz data rate, 3&nbsp;MT/s edit rate) and retains backwards compatibility.<ref>{{cite web |last=Emberson |first=David |date=June 25, 2008 |title=HTX3 specification |url=http://www.hypertransport.org/docs/uploads/HTX3_Specifications.pdf |website=HyperTransport Consortium |page=4 |access-date=August 17, 2008 |url-status=dead |archive-url=https://web.archive.org/web/20120308085016/http://www.hypertransport.org/docs/uploads/HTX3_Specifications.pdf |archive-date=March 8, 2012}}</ref>

=== Testing ===
The "DUT" test connector<ref>{{cite web |last1=Holden |first1=Brian |last2=Meschke |first2=Mike |last3=Abu-Lebdeh |first3=Ziad |last4=D'Orfani |first4=Renato |title=DUT Connector and Test Environment for HyperTransport |url=http://www.hypertransport.org/docs/spec/HTC20021219-0017-0001.pdf |website=HyperTransport Consortium |language=en-US |access-date=November 12, 2022 |url-status=dead |archive-url=https://web.archive.org/web/20060903165421/http://www.hypertransport.org/docs/spec/HTC20021219-0017-0001.pdf |archive-date=September 3, 2006}}</ref> is defined to enable standardized functional test system interconnection.