Editing IBM AS/400 (section)

=== The move to PowerPC ===
{{See also|IBM RS64#History}}

In 1990, IBM Rochester began work to replace the AS/400's original System/38-derived [[48-bit computing|48-bit]] [[complex instruction set computer|CISC]] processors with a 96-bit architecture known as ''C-RISC'' (Commercial [[RISC]]).{{sfnp|Soltis|1997|p={{pn|date=March 2022}}}} Rather than being a clean-slate design, C-RISC would have added RISC-style and [[VLIW]]-style instructions to the AS/400's processor, while maintaining backwards compatibility with the [[System/370]]-style ''Internal Microprogrammed Interface'' (IMPI) instruction set and the [[microcode]] used to implement it.

In 1991, at the request of IBM president [[Jack Kuehler]], a team under the leadership of [[Frank Soltis]] delivered a proposal to adapt the [[64-bit computing|64-bit]] [[PowerPC]] architecture to support the needs of the AS/400 platform.<ref>{{cite book|author1=John Paul Shen|author2=Mikko H. Lipasti|title=Modern Processor Design: Fundamentals of Superscalar Processors|url=https://books.google.com/books?id=ffQqAAAAQBAJ|date=30 July 2013|publisher=Waveland Press |isbn=978-1-4786-1076-2}}</ref> Their extensions to the PowerPC architecture, known as ''Amazon'' (and later as ''PowerPC AS''), were approved by IBM management instead of the C-RISC design for development into the next AS/400 processor architecture.<ref>{{cite magazine|title=Inside the PowerPC AS |url=http://iprodeveloper.com/systems-management/inside-powerpc |date=July 1, 1995 |author1=Adam T. Stallman|author2=Frank G. Soltis |magazine=System iNEWS Magazine|archive-url=https://web.archive.org/web/20130831203807/http://iprodeveloper.com/systems-management/inside-powerpc |archive-date=August 31, 2013}}</ref> These extensions include support for tagged memory,<ref>{{cite web |last=Landau |first=Hugo |url=https://www.devever.net/~hl/ppcas|title=The PowerPC AS Tagged Memory Extensions}}</ref> as well as assistance for decimal arithmetic.<ref>{{cite newsgroup|last=McKenzie |first=Dave |url=https://groups.google.com/g/comp.arch/c/TgbBBxCdK0E/m/HlmFfkymuPcJ|title=Re: Packed decimals |date=December 5, 2000|message-id=fopr2tg596q0s28ibma1bkj05skcdldct8@4ax.com |newsgroup=comp.arch}}</ref>

IBM initially attempted to create a single PowerPC implementation for both AS/400 and high-end RS/6000 systems known as ''Belatrix''.{{sfnp|Soltis|1997|p={{pn|date=March 2022}}}} The Belatrix project proved to be too ambitious, and was cancelled when it became apparent that it would not deliver on schedule. Instead, a pair of AS/400-specific processors were designed at IBM Endicott and IBM Rochester, known as ''Cobra'' (for low end systems) and ''Muskie'' (for high end systems) respectively. These became the initial implementations of the [[IBM RS64]] processor line. The RS64 series continued to be developed as a separate product line at IBM until the [[POWER4]] merged both the RS64 and POWER product lines together.{{sfnp|Soltis|2001|p={{pn|date=October 2023}}}}

Despite the move from IMPI to an entirely different processor architecture, the AS/400's [[IBM i#TIMI|Technology Independent Machine Interface]] (TIMI) mostly hid the changes from users and applications, and transparently recompiled applications for the new processor architecture.<ref name="as400-technical-introduction" /> The port of OS/400 to the PowerPC AS architecture required a rewrite of most of the code below the TIMI due to the use of IMPI microcode to implement significant quantities of the operating system's low level code.{{sfnp|Soltis|2001|p={{pn|date=October 2023}}}} This led to the creation of the System Licensed Internal Code (SLIC) - a new implementation of the lower levels of the operating system mostly written in [[C++]].