Editing IBM RS64 (section)

==RS64-III==
[[File:IBM RS64-III DCM.png|thumb|IBM RS64-III DCM]]
The '''RS64-III''' or '''Pulsar''' was introduced in 1999 at 450&nbsp;MHz. Key changes included larger 128 KiB L1 instruction and data caches, improved [[branch predictor|branch prediction]] accuracy and reduced branch misprediction penalties of zero or one cycle. The RS64-III has a five-stage [[Pipeline (computing)|pipeline]] and a 256-bit wide L2 cache bus, which provided the processor with 14.4 GB/s of bandwidth from the 8 MiB L2 cache, implemented with 225&nbsp;MHz DDR SRAMs.

The RS64-III has 34 million transistors, a die size of 140&nbsp;mm², and is manufactured on the 0.22 μm CMOS 7S process with six levels of [[copper interconnects|copper interconnect]].

In 2000, IBM launched a refined version called '''IStar''' manufactured with a [[Silicon on insulator|SOI]] [[fabrication process]] with copper interconnects, which increased the processor's clock frequency to 600&nbsp;MHz. This was the first processor implemented in this process. Architecturally however, the IStar was identical to Pulsar.