Editing Integrated circuit (section)

=== MOS integrated circuits ===
{{Further|MOSFET applications#MOS integrated circuit}}
{{See also|List of semiconductor scale examples|Mixed-signal integrated circuit|Moore's law|Three-dimensional integrated circuit|Transistor count|Very Large Scale Integration}}

Nearly all modern IC chips are [[MOSFET|metal–oxide–semiconductor]] (MOS) integrated circuits, built from [[MOSFET]]s (metal–oxide–silicon field-effect transistors).<ref name="Kuo">{{cite journal |last1=Kuo |first1=Yue |title=Thin Film Transistor Technology—Past, Present, and Future |journal=The Electrochemical Society Interface |date=1 January 2013 |volume=22 |issue=1 |pages=55–61 |doi=10.1149/2.F06131if |bibcode=2013ECSIn..22a..55K |url=https://www.electrochem.org/dl/interface/spr/spr13/spr13_p055_061.pdf }}</ref> The MOSFET invented at Bell Labs between 1955 and 1960,<ref name="patents.google.com"/><ref>{{Cite journal |last1=Huff |first1=Howard |last2=Riordan |first2=Michael |date=2007-09-01 |title=Frosch and Derick: Fifty Years Later (Foreword) |url=https://iopscience.iop.org/article/10.1149/2.F02073IF |journal=The Electrochemical Society Interface |volume=16 |issue=3 |pages=29 |doi=10.1149/2.F02073IF |issn=1064-8208|url-access=subscription }}</ref><ref name="iopscience.iop.org"/><ref>{{Cite journal |last=KAHNG |first=D. |date=1961 |title=Silicon-Silicon Dioxide Surface Device |url=https://doi.org/10.1142/9789814503464_0076 |journal=Technical Memorandum of Bell Laboratories|pages=583–596 |doi=10.1142/9789814503464_0076 |isbn=978-981-02-0209-5 |url-access=subscription }}</ref><ref>{{Cite book |last=Lojek |first=Bo |title=History of Semiconductor Engineering |date=2007 |publisher=Springer-Verlag Berlin Heidelberg |isbn=978-3-540-34258-8 |location=Berlin, Heidelberg |page=321}}</ref><ref>{{Cite journal |last1=Ligenza |first1=J.R. |last2=Spitzer |first2=W.G. |date=1960 |title=The mechanisms for silicon oxidation in steam and oxygen |url=https://linkinghub.elsevier.com/retrieve/pii/0022369760902195 |journal=Journal of Physics and Chemistry of Solids |language=en |volume=14 |pages=131–136 |doi=10.1016/0022-3697(60)90219-5|bibcode=1960JPCS...14..131L |url-access=subscription }}</ref><ref name="Lojek1202"/> made it possible to build [[very large-scale integration|high-density integrated circuits]].<ref name="computerhistory-transistor">{{cite web |title=Who Invented the Transistor? |author=Laws, David |url=https://www.computerhistory.org/atchm/who-invented-the-transistor/ |website=[[Computer History Museum]] |date=4 December 2013 }}</ref> In contrast to [[bipolar transistor]]s which required a number of steps for the [[p–n junction isolation]] of transistors on a chip, MOSFETs required no such steps but could be easily isolated from each other.<ref name="Bassett53">{{cite book |last1=Bassett |first1=Ross Knox |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |date=2002 |publisher=[[Johns Hopkins University Press]] |isbn=978-0-8018-6809-2 |pages=53–4 |url=https://books.google.com/books?id=Qge1DUt7qDUC&pg=PA53}}</ref> Its advantage for integrated circuits was pointed out by Dawon Kahng in 1961.<ref name="Bassett22">{{cite book |last1=Bassett |first1=Ross Knox |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |date=2007 |publisher=[[Johns Hopkins University Press]] |isbn=9780801886393 |pages=22–25 |url=https://books.google.com/books?id=UUbB3d2UnaAC&pg=PA22}}</ref> The [[list of IEEE milestones]] includes the first integrated circuit by Kilby in 1958,<ref>{{cite web |url=http://www.ieeeghn.org/wiki/index.php/Milestones:First_Semiconductor_Integrated_Circuit_%28IC%29,_1958 |title=Milestones:First Semiconductor Integrated Circuit (IC), 1958 |work=IEEE Global History Network |publisher=IEEE |access-date=3 August 2011}}</ref> Hoerni's planar process and Noyce's planar IC in 1959.<ref>{{Cite web|url=https://ethw.org/Milestones:List_of_IEEE_Milestones|title=Milestones:List of IEEE Milestones – Engineering and Technology History Wiki|website=ethw.org|date=9 December 2020 }}</ref>

The earliest experimental MOS IC to be fabricated was a 16-transistor chip built by Fred Heiman and Steven Hofstein at [[RCA]] in 1962.<ref name="computerhistory-digital">{{cite web |title=Tortoise of Transistors Wins the Race – CHM Revolution |url=https://www.computerhistory.org/revolution/digital-logic/12/279 |website=[[Computer History Museum]] |access-date=22 July 2019}}</ref> [[General Microelectronics]] later introduced the first commercial MOS integrated circuit in 1964,<ref name="computerhistory1964">{{cite web|url=http://www.computerhistory.org/semiconductor/timeline/1964-Commecial.html|title=1964 – First Commercial MOS IC Introduced|website=[[Computer History Museum]]}}</ref> a 120-transistor [[shift register]] developed by Robert Norman.<ref name="computerhistory-digital"/> By 1964, MOS chips had reached higher [[transistor density]] and lower manufacturing costs than [[bipolar junction transistor|bipolar]] chips. MOS chips further increased in complexity at a rate predicted by [[Moore's law]], leading to [[large-scale integration]] (LSI) with hundreds of [[transistor]]s on a single MOS chip by the late 1960s.<ref name="ieee">{{cite journal |last1=Shirriff |first1=Ken |title=The Surprising Story of the First Microprocessors |journal=[[IEEE Spectrum]] |volume=53 |issue=9 |pages=48–54 |date=30 August 2016 |publisher=[[Institute of Electrical and Electronics Engineers]] |url=https://spectrum.ieee.org/the-surprising-story-of-the-first-microprocessors|doi=10.1109/MSPEC.2016.7551353 |s2cid=32003640 |url-access=subscription }}</ref>

{{anchor|The self-aligned gate}}
Following the development of the [[self-aligned gate]] (silicon-gate) MOSFET by Robert Kerwin, [[Donald L. Klein|Donald Klein]] and John Sarace at Bell Labs in 1967,<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=[[Computer History Museum]] |access-date=22 July 2019}}</ref> the first [[silicon-gate]] MOS IC technology with [[self-aligned gate]]s, the basis of all modern [[CMOS]] integrated circuits, was developed at Fairchild Semiconductor by [[Federico Faggin]] in 1968.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=The Silicon Engine |publisher=[[Computer History Museum]] |access-date=13 October 2019}}</ref> The application of MOS LSI chips to [[computing]] was the basis for the first [[microprocessor]]s, as engineers began recognizing that a complete [[computer processor]] could be contained on a single MOS LSI chip. This led to the inventions of the microprocessor and the [[microcontroller]] by the early 1970s.<ref name="ieee"/> During the early 1970s, MOS integrated circuit technology enabled the [[very large-scale integration]] (VLSI) of more than 10,000 transistors on a single chip.<ref>{{cite journal |last1=Hittinger |first1=William C. |title=Metal–Oxide–Semiconductor Technology |journal=Scientific American |date=1973 |volume=229 |issue=2 |pages=48–59 |jstor=24923169 |doi=10.1038/scientificamerican0873-48 |bibcode=1973SciAm.229b..48H }}</ref>

At first, MOS-based computers only made sense when high density was required, such as [[aerospace]] and [[pocket calculator]]s. Computers built entirely from TTL, such as the 1970 [[Datapoint 2200]], were much faster and more powerful than single-chip MOS microprocessors such as the 1972 [[Intel 8008]] until the early 1980s.<ref name="tmx_shirriff">{{cite web | title=The Texas Instruments TMX 1795: the (almost) first, forgotten microprocessor | website=Ken Shirriff's blog | date=1970-10-25 | url=https://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html }}</ref>

Advances in IC technology, primarily [[Semiconductor device fabrication|smaller features]] and larger chips, have allowed [[Transistor count|the number]] of [[MOS transistor]]s in an integrated circuit to double every two years, a trend known as Moore's law. Moore originally stated it would double every year, but he went on to change the claim to every two years in 1975.<ref>{{Cite web|url=https://www.cnet.com/news/moores-law-to-roll-on-for-another-decade/|title=Moore's Law to roll on for another decade|last=Kanellos|first=Michael|website=CNET|date=February 11, 2003}}</ref> This increased capacity has been used to decrease cost and increase functionality. In general, as the feature size shrinks, almost every aspect of an IC's operation improves. The cost per transistor and the [[low-power electronics|switching power consumption]] per transistor goes down, while the [[Computer memory|memory capacity]] and [[clock rate|speed]] go up, through the relationships defined by [[Dennard scaling]] ([[MOSFET scaling]]).<ref>{{cite news |last=Davari |first=Bijan |first2=Robert H. |last2=Dennard |first3=Ghavam G. |last3=Shahidi |title=CMOS scaling for high performance and low power-the next ten years |journal=Proceedings of the IEEE |volume=83 |issue=4 |year=1995 |pages=595–606 |url=http://www.cisl.columbia.edu/courses/spring-2002/ee6930/papers/high_perform_scaling.pdf}}</ref> Because speed, capacity, and power consumption gains are apparent to the end user, there is fierce competition among the manufacturers to use finer geometries. Over the years, transistor sizes have decreased from tens of [[micron]]s in the early 1970s to 10 [[nanometer]]s in 2017<ref>{{Cite web|url=https://news.samsung.com/global/qualcomm-and-samsung-collaborate-on-10nm-process-technology-for-the-latest-snapdragon-835-mobile-processor|title=Qualcomm and Samsung Collaborate on 10nm Process Technology for the Latest Snapdragon 835 Mobile Processor|website=news.samsung.com|access-date=2017-02-11}}</ref> with a corresponding million-fold increase in transistors per unit area. As of 2016, typical chip areas range from a few square [[millimeter]]s to around 600&nbsp;mm<sup>2</sup>, with up to 25 million [[transistor]]s per mm<sup>2</sup>.<ref name=Pascal>{{cite web |url=https://devblogs.nvidia.com/parallelforall/inside-pascal/ |title=Inside Pascal: NVIDIA's Newest Computing Platform|date=2016-04-05}}.  15,300,000,000 transistors in 610 mm<sup>2</sup>.</ref>

The expected shrinking of feature sizes and the needed progress in related areas was forecast for many years by the [[International Technology Roadmap for Semiconductors]] (ITRS). The final ITRS was issued in 2016, and it is being replaced by the [[International Roadmap for Devices and Systems]].<ref>{{cite web |title=International Roadmap for Devices and Systems |publisher=IEEE |year=2016 |url=https://rebootingcomputing.ieee.org/images/files/pdf/rc_irds.pdf}}</ref>

Initially, ICs were strictly electronic devices. The success of ICs has led to the integration of other technologies, in an attempt to obtain the same advantages of small size and low cost. These technologies include mechanical devices, optics, and sensors.
* [[Charge-coupled device]]s, and the closely related [[active-pixel sensor]]s, are chips that are sensitive to [[light]]. They have largely replaced [[photographic film]] in scientific, medical, and consumer applications. Billions of these devices are now produced each year for applications such as cellphones, tablets, and digital cameras. This sub-field of ICs won the Nobel Prize in 2009.<ref name= CcdNobel >{{citation | title = The Nobel Prize in Physics 2009 | url = http://nobelprize.org/nobel_prizes/physics/laureates/2009/index.html | publisher = Nobel Foundation | date = 2009-10-06 | access-date = 2009-10-06}}.</ref>
* Very small mechanical devices driven by electricity can be integrated onto chips, a technology known as [[microelectromechanical systems]] (MEMS). These devices were developed in the late 1980s<ref>{{cite conference |title=A decade of MEMS and its future |author=Fujita, H. |conference= Tenth Annual International Workshop on Micro Electro Mechanical Systems |year=1997 |doi=10.1109/MEMSYS.1997.581729 }}</ref> and are used in a variety of commercial and military applications. Examples include [[DLP projector]]s, [[inkjet printer]]s, and [[accelerometer]]s and [[MEMS gyroscope]]s used to deploy automobile [[airbag]]s.
* Since the early 2000s, the integration of optical functionality ([[optical computing]]) into silicon chips has been actively pursued in both academic research and in industry resulting in the successful commercialization of silicon based integrated optical transceivers combining optical devices (modulators, detectors, routing) with CMOS based electronics.<ref>{{cite journal|author = Narasimha, A. |title = A 40-Gb/s QSFP optoelectronic transceiver in a 0.13 µm CMOS silicon-on-insulator technology|year = 2008|journal = Proceedings of the Optical Fiber Communication Conference (OFC)|page = OMK7|url=http://www.opticsinfobase.org/abstract.cfm?URI=OFC-2008-OMK7|display-authors=etal}}</ref> [[Photonic integrated circuit]]s that use light such as Lightelligence's PACE (Photonic Arithmetic Computing Engine) also being developed, using the emerging field of physics known as [[photonics]].<ref>{{cite web | url=https://physicsworld.com/a/optical-chipmaker-focuses-on-high-performance-computing/ | title=Optical chipmaker focuses on high-performance computing | date=7 April 2022 }}</ref>
* Integrated circuits are also being developed for [[sensor]] applications in [[implant (medicine)|medical implants]] or other [[bioelectronics|bioelectronic]] devices.<ref name= Birkholz2015>{{cite journal | url = https://www.researchgate.net/publication/282052331 | title = Technology modules from micro- and nano-electronics for the life sciences | journal = WIREs Nanomed. Nanobiotech. | volume = 8 |issue=3 | pages = 355–377 | year = 2016 | doi = 10.1002/wnan.1367 |pmid=26391194 | last1 = Birkholz | first1 = M. | last2 = Mai | first2 = A. | last3 = Wenger | first3 = C. | last4 = Meliani | first4 = C. | last5 = Scholz | first5 = R. }}</ref> Special sealing techniques have to be applied in such biogenic environments to avoid [[corrosion]] or [[biodegradation]] of the exposed semiconductor materials.<ref name="Graham2011">{{cite journal | title = Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors | journal = Sensors | volume = 11 |issue=5 | pages = 4943–4971 | year = 2011 | doi = 10.3390/s110504943 |pmid=22163884 |pmc=3231360 | last1 = Graham | first1 = Anthony H. D. | last2 = Robbins | first2 = Jon | last3 = Bowen | first3 = Chris R. | last4 = Taylor | first4 = John | bibcode = 2011Senso..11.4943G | doi-access = free }}</ref>
{{As of|2018}}, the vast majority of all transistors are [[MOSFET]]s fabricated in a single layer on one side of a chip of silicon in a flat two-dimensional [[planar process]]. Researchers have produced prototypes of several promising alternatives, such as:
* various approaches to stacking several layers of transistors to make a [[three-dimensional integrated circuit]] (3DIC), such as [[through-silicon via]], "monolithic 3D",<ref>{{cite web |last=Or-Bach |first=Zvi |date=December 23, 2013 |url=http://semimd.com/blog/2013/12/23/why-soi-is-the-future-technology-of-semiconductors/ |title=Why SOI is the Future Technology of Semiconductors |website=semimd.com |archive-url=https://web.archive.org/web/20141129104851/http://semimd.com/blog/2013/12/23/why-soi-is-the-future-technology-of-semiconductors/ |archive-date=29 November 2014 |url-status=usurped}}.
2013.</ref> stacked wire bonding,<ref>{{cite web | title=Samsung's Eight-Stack Flash Shows up in Apple's iPhone 4 | website=Siliconica | date=2010-09-13 | url=https://sst.semiconductor-digest.com/chipworks_real_chips_blog/2010/09/13/samsungs-eight-stack-flash-shows-up-in-apples-iphone-4/}}</ref> and other methodologies.
* transistors built from other materials: [[graphene transistor]]s, [[molybdenite#Semiconductor|molybdenite transistors]], [[carbon nanotube field-effect transistor]], [[gallium nitride]] transistor, transistor-like [[nanowire#Electronic devices|nanowire electronic devices]], [[organic field-effect transistor]], etc.
* fabricating transistors over the entire surface of a small sphere of silicon.<ref>{{cite journal|url=http://www.natureinterface.com/e/ni07/P058-059/|title=Spherical semiconductor radio temperature sensor|journal=Nature Interface|year=2002|pages=58–59|volume=7|author=Yamatake Corporation|archive-url=https://web.archive.org/web/20090107144008/http://www.natureinterface.com/e/ni07/P058-059/|archive-date=7 January 2009}}</ref><ref>
{{Citation
| last       = Takeda
| first      = Nobuo
| title      = MEMS applications of Ball Semiconductor Technology
| url        = http://asia.stanford.edu/events/spring01/slides/takedaslides.pdf
| archive-url  = https://web.archive.org/web/20150101122744/http://asia.stanford.edu/events/spring01/slides/takedaslides.pdf
| archive-date = 2015-01-01
}}
</ref>
* modifications to the substrate, typically to make "[[transistor#Flexible transistors|flexible transistors]]" for a [[flexible display]] or other [[flexible electronics]], possibly leading to a [[roll-away computer]].

As it becomes more difficult to manufacture ever smaller transistors, companies are using [[multi-chip module]]s/[[chiplet]]s, [[three-dimensional integrated circuit]]s, [[package on package]], [[High Bandwidth Memory]] and [[through-silicon via]]s with die stacking to increase performance and reduce size, without having to reduce the size of the transistors. Such techniques are collectively known as [[Advanced packaging (semiconductors)|advanced packaging]].<ref>{{Cite web|url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/|title=Advanced Packaging}}</ref> Advanced packaging is mainly divided into 2.5D and 3D packaging. 2.5D describes approaches such as multi-chip modules while 3D describes approaches where dies are stacked in one way or another, such as package on package and high bandwidth memory. All approaches involve 2 or more dies in a single package.<ref>{{Cite web|url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/2-5d-ic/|title=2.5D|work=Semiconductor Engineering}}</ref><ref>{{Cite web|url=https://semiengineering.com/knowledge_centers/packaging/advanced-packaging/3d-ics/|title=3D ICs|work=Semiconductor Engineering}}</ref><ref>{{cite web | title=Chiplet | website=WikiChip | date=2021-02-28 | url=https://en.wikichip.org/wiki/chiplet }}</ref><ref>{{Cite magazine|url=https://www.wired.com/story/keep-pace-moores-law-chipmakers-turn-chiplets/|title=To Keep Pace With Moore's Law, Chipmakers Turn to 'Chiplets'|magazine=Wired|date=11 June 2018}}</ref><ref>{{cite web | last=Schodt | first=Christopher | title=This is the year of the CPU 'chiplet' | website=Engadget | date=2019-04-16 | url=https://www.engadget.com/2019-04-16-upscaled-cpu-chiplet.html }}</ref> Alternatively, approaches such as [[3D NAND]] stack multiple layers on a single die. A technique has been demonstrated to include microfluidic cooling on integrated circuits, to improve cooling performance<ref>{{cite web | url=https://spectrum.ieee.org/codesigning-electronics-and-microfluidics-for-a-cooling-boost | title=Building Power Electronics with Microscopic Plumbing Could Save Enormous Amounts of Money - IEEE Spectrum }}</ref> as well as peltier thermoelectric coolers on solder bumps, or thermal solder bumps used exclusively for heat dissipation, used in [[flip-chip]].<ref>{{cite web | url=https://arstechnica.com/gadgets/2008/01/startup-shrinks-the-peltier-cooler-and-puts-it-inside-the-chip-package/ | title=Startup shrinks Peltier cooler, puts it in the chip package | date=10 January 2008 }}</ref><ref>{{cite web | url=https://sst.semiconductor-digest.com/2005/07/wire-bond-vs-flip-chip-packaging/ | title=Wire Bond Vs. Flip Chip Packaging &#124; Semiconductor Digest | date=10 December 2016 }}</ref>