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Intel 8008
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==Instruction set== Instructions are all one to three bytes long, consisting of an initial opcode byte, followed by up to two bytes of operands which can be an immediate operand or a program address. Instructions operate on 8-bits only; there are no 16-bit operations. There is only one mechanism to address data memory: indirect addressing pointed to by a concatenation of the H and L registers, referenced as M. The 8008 does, however, support 14-bit program addresses. It has automatic CAL and RET instructions for multi-level subroutine calls and returns which can be conditionally executed, like jumps. Eight one-byte call instructions (RST) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke interrupt service routines, but can employed as fast calls. Direct copying may be made between any two registers or a register and memory. Eight math/logic functions are supported between the accumulator (A) and any register, memory, or an immediate value. Results are always deposited in A. Increments and decrements are supported for most registers but, curiously, not A. Register A does, however, support four different rotate instructions. All instructions are executed in 3 to 11 states. Each state requires two clocks. {|class="wikitable" style="text-align:center" !colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| States ||rowspan=2| Description |- ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 |- | 0 || 0 || 0 || 0 || 0 || 0 || 0 || X || — || — ||align=left| {{mono|HLT}} || 4 ||align=left| Halt |- | 0 || 0 ||colspan=3|DDD || 0 || 0 || 0 || — || — ||align=left| {{mono|INr}} || 5 ||align=left| DDD β DDD + 1 (except A and M) |- | 0 || 0 ||colspan=3|DDD || 0 || 0 || 1 || — || — ||align=left| {{mono|DCr}} || 5 ||align=left| DDD β DDD - 1 (except A and M) |- | 0 || 0 || 0 || 0 || 0 || 0 || 1 || 0 || — || — ||align=left| {{mono|RLC}} || 5 ||align=left| A<sub>1-7</sub> β A<sub>0-6</sub>; A<sub>0</sub> β Cy β A<sub>7</sub> |- | 0 || 0 ||colspan=3|CC || 0 || 1 || 1 || — || — ||align=left| {{mono|Rcc (RET conditional)}} || 3/5 ||align=left| If cc true, P β (stack) |- | 0 || 0 ||colspan=3|ALU || 1 || 0 || 0 || ''data'' || — ||align=left| {{mono|ADI ACI SUI SBI NDI XRI ORI CPI ''data''}} || 8 ||align=left| A β A [ALU operation] data |- | 0 || 0 ||colspan=3|N || 1 || 0 || 1 || — || — ||align=left| {{mono|RST ''n''}} || 5 ||align=left| (stack) β P, P β N x 8 |- | 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || — ||align=left| {{mono|LrI ''data'' (Load r with immediate data)}} || 8/9 ||align=left| DDD β data |- | 0 || 0 || X || X || X || 1 || 1 || 1 || — || — ||align=left| {{mono|RET}} || 5 ||align=left| P β (stack) |- | 0 || 0 || 0 || 0 || 1 || 0 || 1 || 0 || — || — ||align=left| {{mono|RRC}} || 5 ||align=left| A<sub>0-6</sub> β A<sub>1-7</sub>; A<sub>7</sub> β Cy β A<sub>0</sub> |- | 0 || 0 || 0 || 1 || 0 || 0 || 1 || 0 || — || — ||align=left| {{mono|RAL}} || 5 ||align=left| A<sub>1-7</sub> β A<sub>0-6</sub>; Cy β A<sub>7</sub>; A<sub>0</sub> β Cy |- | 0 || 0 || 0 || 1 || 1 || 0 || 1 || 0 || — || — ||align=left| {{mono|RAR}} || 5 ||align=left| A<sub>0-6</sub> β A<sub>1-7</sub>; Cy β A<sub>0</sub>; A<sub>7</sub> β Cy |- | 0 || 1 ||colspan=3|CC || 0 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|Jcc ''add'' (JMP conditional)}}|| 9/11 ||align=left| If cc true, P β add |- | 0 || 1 || 0 || 0 ||colspan=3|port || 1 || — || — ||align=left| {{mono|INP ''port''}} || 8 ||align=left| A β Port (ports 0-7 only) |- | 0 || 1 ||colspan=5|port || 1 || — || — ||align=left| {{mono|OUT ''port''}} || 6 ||align=left| Port β A (ports 8-31 only) |- | 0 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|Ccc ''add'' (CAL conditional)}}|| 9/11 ||align=left| If cc true, (stack) β P, P β add |- | 0 || 1 || X || X || X || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|JMP ''add''}} || 11 ||align=left| P β add |- | 0 || 1 || X || X || X || 1 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| {{mono|CAL ''add''}} || 11 ||align=left| (stack) β P, P β add |- | 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || — || — ||align=left| {{mono|ADr ACr SUr SBr NDr XRr ORr CPr}} || 5/8 ||align=left| A β A [ALU operation] SSS |- | 1 || 1 ||colspan=3|DDD ||colspan=3|SSS || — || — ||align=left| {{mono|Lds (Load d with s)}} ||5/7/8 ||align=left| DDD β SSS |- | 1 || 1 || 1 || 1 || 1 || 1 || 1 || 1 || — || — ||align=left| {{mono|HLT}} || 4 ||align=left| Halt |- ! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || States || Description |- !colspan=13| |- !colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU |- |colspan=5| A || 0 || 0 || 0 ||colspan=2|FC, C false ||align=left| {{mono|ADr ADI (A β A + arg)}} |- |colspan=5| B || 0 || 0 || 1||colspan=2|FZ, Z false||align=left| {{mono|ACr ACI (A β A + arg + Cy)}} |- |colspan=5| C || 0 || 1 || 0||colspan=2|FS, S false ||align=left| {{mono|SUr SUI (A β A - arg)}} |- |colspan=5| D || 0 || 1 || 1||colspan=2|FP, P odd ||align=left| {{mono|SBr SBI (A β A - arg - Cy)}} |- |colspan=5| E || 1 || 0 || 0||colspan=2|TC, C true ||align=left| {{mono|NDr NDI (A β A β§ arg)}} |- |colspan=5| H || 1 || 0 || 1||colspan=2|TZ, Z true ||align=left| {{mono|XRr XRI (A β A β» arg)}} |- |colspan=5| L || 1 || 1 || 0||colspan=2|TS, S true ||align=left| {{mono|ORr ORI (A β A β¨ arg)}} |- |colspan=5| M || 1 || 1 || 1||colspan=2|TP, P even ||align=left| {{mono|CPr CPI (A - arg)}} |- !colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU |} ===Code example 1=== [[File:Intel 8008 wafer.jpg|thumb|Intel 8008 wafer and two processors, closed and open]] The following 8008 [[assembly language|assembly]] source code is for a subroutine named <code>MEMCPY</code> that copies a block of data bytes of a given size from one location to another. Intel's 8008 assembler supported only + and - operators. This example borrows the 8080's assembler AND and SHR (shift right) operators to select the low and high bytes of a 14-bit address for placement into the 8 bit registers. A contemporaneous 8008 programmer was expected to calculate the numbers and type them in for the assembler. <!--NOTE: This is not intended to be optimized code, but to illustrate the variety of instructions available on the CPU--> {| | <pre> 001700 000 001701 000 001702 000 001703 000 001704 000 001705 000 002000 066 304 002002 056 003 002004 327 002005 060 002006 317 002007 302 002010 261 002011 053 002012 302 002013 024 001 002015 320 002016 301 002017 034 000 002021 310 002022 066 300 002024 056 003 002026 302 002027 207 002030 340 002031 060 002032 301 002033 217 002034 350 002035 364 002036 337 002037 066 302 002041 056 003 002043 302 002044 207 002045 340 002046 060 002047 301 002050 217 002051 350 002052 364 002053 373 002054 104 007 004 002057 </pre> | <syntaxhighlight lang="nasm"> ; MEMCPY -- ; Copy a block of memory from one location to another. ; ; Entry parameters ; SRC: 14-bit address of source data block ; DST: 14-bit address of target data block ; CNT: 14-bit count of bytes to copy ORG 1700Q ;Data at 001700q SRC DFB 0 ;SRC, low byte DFB 0 ; high byte DST DFB 0 ;DST, low byte DFB 0 ; high byte CNT DFB 0 ;CNT, low byte DFB 0 ; high byte ORG 2000Q ;Code at 002000q MEMCPY LLI CNT AND 255 ;HL = addr(CNT) LHI CNT SHR 8 ;(AND and SHR not supported) LCM ;BC = CNT INL LBM LOOP LAC ;If BC = 0, ORB RTZ ;Return DECCNT LAC ;BC = BC - 1 SUI 1 LCA LAB SBI 0 LBA GETSRC LLI SRC AND 255 ;HL = addr(SRC) LHI SRC SHR 8 LAC ;HL = SRC + BC ADM ;E = C + (HL) LEA ;(lower sum) INL ;point to upper SRC LAB ACM ;H = B + (HL) + CY LHA ;(upper sum) LLE ;L = E LDM ;Load D from (HL) GETDST LLI DST AND 255 ;HL = addr(DST) LHI DST SHR 8 LAC ;HL = DST + BC ADM ;ADD code same as above LEA INL LAB ACM LHA LLE LMD ;Store D to (HL) JMP LOOP ;Repeat the loop END </syntaxhighlight> |} In the code above, all values are given in octal. Locations {{code|SRC}}, {{code|DST}}, and {{code|CNT}} are 16-bit parameters for the subroutine named {{code|MEMCPY}}. In actuality, only 14 bits of the values are used, since the CPU has only a 14-bit addressable memory space. The values are stored in [[little-endian]] format, although this is an arbitrary choice, since the CPU is incapable of reading or writing more than a single byte into memory at a time. Since there is no instruction to load a register directly from a given memory address, the HL register pair must first be loaded with the address, and the target register can then be loaded from the M operand, which is an indirect load from the memory location in the HL register pair. The BC register pair is loaded with the {{code|CNT}} parameter value and decremented at the end of the loop until it becomes zero. Note that most of the instructions used occupy a single 8-bit opcode. ===Code example 2=== The following 8008 assembly source code is for a simplified subroutine named MEMCPY2 that copies a block of data bytes from one location to another. By reducing the byte counter to 8 bits, there is enough room to load all the subroutine parameters into the 8008's register file. <!--This routine was assembled by brain and might contain errors--> {| | <pre> 002000 307 002001 206 015 004 002004 370 002005 206 015 004 002010 021 002011 110 000 004 002014 007 002015 316 002016 364 002017 341 002020 315 002021 353 002022 331 002023 040 002024 013 002025 030 002026 007 002027 </pre> | <syntaxhighlight lang="nasm"> ; MEMCPY2 -- ; Copy a block of memory from one location to another ; ; Entry parameters in registers ; HL: 14-bit address of source data block ; DE: 14-bit address of target data block ; C: 8-bit count of bytes to copy. (1 to 256 bytes) ORG 2000Q ;Code at 002000q MEMCPY2 LAM ;Read source byte into A CAL XCHGI ;Exchange HL<->DE and increment DE LMA ;Save A to target byte CAL XCHGI ;Exchange HL<->DE and increment DE DCC ;Decrement byte counter JFZ MEMCPY2 ;Continue for all bytes RET ;Exchange DE and HL register pairs then increment DE as 16 bits XCHGI LBL ;Exchange L and E LLE LEB LBH ;Exchange H and D LHD LDB INE ;Inc E, low byte of DE RFZ ;Return if no carry IND ;Otherwise inc high byte D RET END </syntaxhighlight> |}
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