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Intel iAPX 432
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===Impact and similar designs=== The iAPX 432 was one of the first systems to implement the new [[IEEE-754]] Standard for Floating-Point Arithmetic.<ref>{{cite web|last1=Vickery|first1=Christopher|title=IEEE-754 Reference Material|url=http://babbage.cs.qc.cuny.edu/IEEE-754.old/References.xhtml|access-date=Dec 5, 2015|archive-date=December 1, 2011|archive-url=https://web.archive.org/web/20111201211023/http://babbage.cs.qc.cuny.edu/IEEE-754.old/References.xhtml|url-status=dead}}</ref> An outcome of the failure of the 432 was that microprocessor designers concluded that object support in the chip leads to a complex design that will invariably run slowly, and the 432 was often cited as a counter-example by proponents of [[RISC]] designs. However, some hold that the OO support was not the primary problem with the 432, and that the implementation shortcomings (especially in the compiler) mentioned above would have made any CPU design slow. Since the iAPX 432 there has been only one other attempt at a similar design, the [[Rekursiv]] processor, although the [[INMOS Transputer]]'s process support was similar — and very fast.{{Citation needed|date=March 2016}} Intel had spent considerable time, money, and [[mindshare]] on the 432, had a skilled team devoted to it, and was unwilling to abandon it entirely after its failure in the marketplace. A new architect—[[Glenford Myers]]—was brought in to produce an entirely new architecture and implementation for the core processor, which would be built in a joint [[Intel]]/[[Siemens]] project (later [[BiiN]]), resulting in the [[Intel i960|i960]]-series processors. The i960 RISC subset became popular for a time in the embedded processor market, but the high-end 960MC and the tagged-memory 960MX were marketed only for military applications. According to the ''New York Times'', Intel's collaboration with HP on the [[Itanium|Merced processor (later known as Itanium)]] was the company's comeback attempt for the very high-end market.<ref name="MARKOFF"/>
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