Editing JTAG (section)

== Electrical characteristics ==

A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added. The four and five pin interfaces are designed so that multiple chips on a board can have their JTAG lines [[Daisy chain (electrical engineering)|daisy-chained]] together if specific conditions are met.<ref>{{cite web|url=http://www.jtagtest.com/faq/jtag-ieee-1149-1/under-what-conditions-can-i-daisy-chain-jtag|title=FAQ: Under what conditions can I daisy-chain JTAG?|website=www.jtagtest.com}}</ref> The two-pin interface is designed so that multiple chips can be connected in a [[star topology]]. In either case, a [[test probe]] need only connect to a single JTAG port to have access to all chips on a [[circuit board]].

=== Daisy-chained JTAG (IEEE 1149.1) ===
[[Image:Jtag chain.svg|center|Example of JTAG chain. Test reset signal is not shown]]

The connector pins are:

#'''TDI''' (Test Data In)
#'''TDO''' (Test Data Out)
#'''TCK''' (Test Clock)
#'''TMS''' (Test Mode Select)
#'''TRST''' (Test Reset) optional.

The TRST pin is an optional active-low reset to the test logic, usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by switching to the reset state synchronously, using TCK and TMS. Note that resetting test logic doesn't necessarily imply resetting anything else. There are generally some processor-specific JTAG operations which can reset all or part of the chip being debugged.

Since only one data line is available, the protocol is [[Serial communications|serial]]. The clock input is at the TCK pin. One bit of data is transferred in from TDI, and out to TDO per TCK rising clock edge. Different instructions can be loaded. Instructions for typical ICs might read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips).

As with any clocked signal, data presented to TDI must be valid for some chip-specific ''Setup'' time before and ''Hold'' time after the relevant (here, rising) clock edge. TDO data is valid for some chip-specific time after the falling edge of TCK.

The maximum operating frequency of TCK varies depending on all chips in the chain (the lowest speed must be used), but it is typically 10-100&nbsp;MHz (100-10 ns per bit). Also TCK frequencies depend on board layout and JTAG adapter capabilities and state. One chip might have a 40&nbsp;MHz JTAG clock, but only if it is using a 200&nbsp;MHz clock for non-JTAG operations; and it might need to use a much slower clock when it is in a low-power mode. Accordingly, some JTAG adapters have ''adaptive clocking'' using an RTCK (Return TCK) signal. Faster TCK frequencies are most useful when JTAG is used to transfer much data, such as when storing a program executable into [[flash memory]].

Clocking changes on TMS steps through a standardized JTAG [[state machine]]. The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register.

JTAG platforms often add signals to the handful defined by the IEEE 1149.1 specification. A System Reset (SRST) signal is quite common, letting debuggers reset the whole system, not just the parts with JTAG support. Sometimes there are event signals used to trigger activity by the host or by the device being monitored through JTAG; or, perhaps, additional control lines.

Even though few consumer products provide an explicit JTAG port connector, the connections are often available on the [[printed circuit board]] as a remnant from development [[prototyping]] and/or production. When exploited, these connections often provide the most viable means for [[reverse engineering]].

=== Reduced pin count JTAG (IEEE 1149.7) ===
[[File:Example of reduced pin count JTAG interface.svg|thumb|Example of JTAG with reduced pin count]]

Reduced pin count JTAG uses only two wires, a clock wire and a data wire. This is defined as part of the IEEE 1149.7 standard.<ref name="ieee-1149.7"/> The connector pins are:

#'''TMSC''' (Test Serial Data)
#'''TCK''' (Test Clock)

It is called cJTAG for compact JTAG.

The two-wire interface reduced pressure on the number of pins, and devices can be connected in a [[star topology]].<ref>{{cite web|url=https://www.corelis.com/education/design-testability-tips-guidelines/major-benefits-ieee-1149-7/|title=Major Benefits of IEEE 1149.7|archive-url=https://web.archive.org/web/20190212011706/https://www.corelis.com/education/design-testability-tips-guidelines/major-benefits-ieee-1149-7/|archive-date=2019-02-12}}</ref> The star topology enables some parts of the system to be powered down, while others can still be accessed over JTAG; a daisy chain requires all JTAG interfaces to be powered. Other two-wire interfaces exist, such as [[#Similar interface standards|Serial Wire Debug]] (SWD) and [[Spy-Bi-Wire]] (SBW).