Editing Logical effort (section)

==Examples==

===Delay in an inverter===

[[Image:CMOS Inverter.svg|right|thumb|A CMOS inverter circuit.]]

By definition, the logical effort ''g'' of an inverter is 1.  If the inverter drives an equivalent inverter, the electrical effort ''h'' is also 1.

The parasitic delay ''p'' of an inverter is also 1 (this can be found by considering the [[Elmore delay]] model of the inverter).

Therefore, the total normalised delay of an inverter driving an equivalent inverter is

:<math>d = gh + p = (1)(1) + 1 = 2</math>

===Delay in NAND and NOR gates===

The logical effort of a two-input NAND gate is calculated to be ''g'' = 4/3 because a NAND gate with input capacitance 4 can drive the same current as the inverter can, with input capacitance 3.  Similarly, the logical effort of a two-input NOR gate can be found to be ''g'' = 5/3.  Due to the lower logical effort, NAND gates are typically preferred to NOR gates.

For larger gates, the logical effort is as follows:
{|cellspacing=10
|+ Logical effort for inputs of static CMOS gates, with
gamma = 2
|
!colspan=6| Number of Inputs
|-
!Gate type!!1!!2!!3!!4!!5!!n
|-
|Inverter
|1
| N/A
| N/A
| N/A
| N/A
| N/A
|-
|NAND
| N/A
|<math>\frac{4}{3}</math>
|<math>\frac{5}{3}</math>
|<math>\frac{6}{3}</math>
|<math>\frac{7}{3}</math>
|<math>\frac{n + 2}{3}</math>
|-
|NOR
| N/A
|<math>\frac{5}{3}</math>
|<math>\frac{7}{3}</math>
|<math>\frac{9}{3}</math>
|<math>\frac{11}{3}</math>
|<math>\frac{2n + 1}{3}</math>
|}

The normalised parasitic delay of NAND and NOR gates is equal to the number of inputs.

Therefore, the normalised delay of a two-input NAND gate driving an identical copy of itself (such that the electrical effort is 1) is

:<math>d = gh + p = (4/3)(1) + 2 = 10/3</math>

and for a two-input NOR gate, the delay is

:<math>d = gh + p = (5/3)(1) + 2 = 11/3</math>

<!-- Examples are needed of multistage circuits, in particular achieving the minimum delay of a path. -->