Editing MMX (instruction set) (section)

==Successors==
AMD, a competing [[x86]] microprocessor vendor, enhanced Intel's MMX with their own [[3DNow!]] instruction set. 3DNow is best known for adding single-precision (32-bit) floating-point support to the SIMD instruction-set, among other integer and more general enhancements.

Following MMX, Intel's next major x86 extension was the [[Streaming SIMD Extensions]] (SSE), introduced with the [[Pentium III]] family<ref name=WP.99>{{cite news |last=Kay |first=Alan S. |date=February 26, 1999 |title=Pentium III: Buy the Numbers? |url=https://www.washingtonpost.com/archive/business/technology/1999/02/26/pentium-iii-buy-the-numbers/b449fa0b-071a-41f7-a623-4781a3409a62/ |newspaper=[[The Washington Post]] |access-date=January 13, 2019 |archive-date=April 15, 2019 |archive-url=https://web.archive.org/web/20190415153149/https://www.washingtonpost.com/archive/business/technology/1999/02/26/pentium-iii-buy-the-numbers/b449fa0b-071a-41f7-a623-4781a3409a62/ |url-status=live }}</ref> in 1999,<ref>{{cite web |title=Microprocessor Hall of Fame |url=http://www.intel.com/museum/online/hist_micro/hof/ |website=Intel Museum |url-status=dead |archive-url=https://web.archive.org/web/20080406154333/http://www.intel.com/museum/online/hist_micro/hof/ |archive-date=2008-04-06
}}</ref> roughly a year after AMD's 3DNow! was introduced.

SSE addressed the core shortcomings of MMX (inability to mix integer-SIMD ops with any floating-point ops) by creating a new 128-bit wide register file (XMM0–XMM7) and new SIMD instructions for it. Like 3DNow!, SSE focused exclusively on single-precision floating-point operations (32-bit); integer SIMD operations were still performed using the MMX register and instruction set. However, the new XMM register-file allowed SSE SIMD-operations to be freely mixed with either MMX or x87 FPU ops.

''Streaming SIMD Extensions 2'' ([[SSE2]]), introduced with the [[Pentium 4]], further extended the x86 SIMD instruction set with integer (8/16/32 bit) and double-precision floating-point data support for the XMM register file. SSE2 also allowed the MMX ''operation codes'' ([[opcode]]s) to use XMM register operands, extended to even wider YMM and ZMM registers by later SSE revisions.