Editing Magnetic-core memory (section)

==Description==
[[File:Coincident-current magnetic core.svg|thumb|left|Diagram of a 4×4 plane of magnetic core memory in an X/Y line coincident-current setup. X and Y are drive lines, S is sense, Z is inhibit. Arrows indicate the direction of current for writing.]]
[[File:KL Kernspeicher Makro 1.jpg|thumb|right|Close-up of a core plane. The distance between the rings is roughly 1 mm (0.04 in). The green horizontal wires are X; the Y wires are dull brown and vertical, toward the back. The sense wires are diagonal, colored orange, and the inhibit wires are vertical twisted pairs.]]

The term "core" comes from conventional [[transformer]]s whose windings surround a [[magnetic core]]. In core memory, the wires pass once through any given core&mdash;they are single-turn devices. The properties of materials used for memory cores are dramatically different from those used in power transformers. The magnetic material for a core memory requires a high degree of magnetic [[remanence]], the ability to stay highly magnetized, and a low [[coercivity]] so that less energy is required to change the magnetization direction. The core can take two states, encoding one [[bit]]. The core memory contents are retained even when the memory system is powered down ([[non-volatile memory]]). However, when the core is read, it is reset to a "zero" value. Circuits in the computer memory system then restore the information in an immediate re-write cycle.

===How core memory works===
[[File:PDP-8 core memory driver module 1.jpg|thumb|One of three inter-connected modules that make up an Omnibus-based (PDP 8/e/f/m) PDP-8 core memory plane.]]
[[File:PDP-8 core memory.jpg|thumb|One of three inter-connected modules that make up an Omnibus-based PDP-8 core memory plane.  This is the middle of the three and contains the array of actual ferrite cores.]]
[[File:PDP-8 core memory driver module 2.jpg|thumb|One of three inter-connected modules that make up an Omnibus-based PDP-8 core memory plane.]]

The most common form of core memory, ''X/Y line coincident-current'', used for the main memory of a computer, consists of a large number of small [[toroid]]al [[ferrimagnetic]] [[ceramic]] [[Ferrite (magnet)|ferrite]]s (''cores'') held together in a grid structure (organized as a "stack" of layers called ''planes''), with wires woven through the holes in the cores' centers. In early systems there were four wires: ''X'', ''Y'', ''Sense'', and ''Inhibit'', but later cores combined the latter two wires into one ''Sense/Inhibit'' line.<ref name=US3329940 /> Each toroid stored one [[bit]] (0 or 1). One bit in each plane could be accessed in one cycle, so each machine [[Word (computer architecture)|word]] in an array of words was spread over a "stack" of planes. Each plane would manipulate one bit of a word in [[parallel computing|parallel]], allowing the full word to be read or written in one cycle.

Core relies on the square hysteresis loop properties of the ferrite material used to make the toroids. An electric current in a wire that passes through a core creates a magnetic field. Only a [[magnetic field]] greater than a certain intensity ("select") can cause the core to change its magnetic polarity. To select a memory location, one of the X and one of the Y lines are driven with half the current ("half-select") required to cause this change. Only the combined magnetic field generated where the X and Y lines cross (the [[logical conjunction]]) is sufficient to change the state; other cores will see only half the needed field ("half-selected"), or none at all. By driving the current through the wires in a particular direction, the resulting [[electromagnetic induction|induced]] field forces the selected core's magnetic flux to circulate in one direction or the other (clockwise or counterclockwise). One direction is a stored ''1'', while the other is a stored ''0''.

The toroidal shape of a core is preferred since the magnetic path is closed, there are no magnetic poles and thus very little external flux. This allows the cores to be packed closely together without their magnetic fields interacting. The alternating 45-degree positioning used in early core arrays was necessitated by the diagonal sense wires. With the elimination of these diagonal wires, tighter packing was possible.<ref name=US3711839 />

===Reading and writing===
[[File:Ringkernspeicher hysteresekurven.agr.svg|thumb|right|Diagram of the [[Magnetic hysteresis|hysteresis]] curve for a magnetic memory core during a read operation. Sense line current pulse is high ("1") or low ("0") depending on original magnetization state of the core.]]

The access time plus the time to rewrite is the '''memory cycle time'''.

====Reading====
To read a bit of core memory, the circuitry tries to flip the bit to the polarity assigned to the 0 state, by driving the selected X and Y lines that intersect at that core.

* If the bit was already 0, the physical state of the core is unaffected.
* If the bit was previously 1, then the core changes magnetic polarity. This change, after a delay, induces a voltage pulse into the Sense line.

The detection of such a pulse means that the bit had most recently contained a 1. Absence of the pulse means that the bit had contained a 0. The delay in sensing the voltage pulse is called the '''access time''' of the core memory.

Following any such read, the bit contains a 0. This illustrates why a core memory access is called a ''destructive read'': Any operation that reads the contents of a core erases those contents, and they must immediately be recreated.

====Writing====
To write a bit of core memory, the circuitry assumes there has been a read operation and the bit is in the 0 state.

* To write a 1 bit, the selected X and Y lines are driven, with current in the opposite direction as for the read operation. As with the read, the core at the intersection of the X and Y lines changes magnetic polarity.
* To write a 0 bit, two methods can be applied. The first one is the same as reading process with current in the original direction. The second has reversed logic. To write a 0 bit, in other words, is to inhibit the writing of a 1 bit. The same amount of current is also sent through the Inhibit line. This reduces the net current flowing through the respective core to half the select current, inhibiting change of polarity.

====Combined sense and inhibit====
The Sense wire is used only during the read, and the Inhibit wire is used only during the write. For this reason, later core systems combined the two into a single wire, and used circuitry in the memory controller to switch the function of the wire.

However, when Sense wire crosses too many cores, the half select current can also induce a considerable voltage across the whole line due to the superposition of the voltage at each single core. This potential risk of "misread" limits the minimum number of Sense wires.

Increasing Sense wires also requires more decode circuitry.

====Combined read and write with modify====
Core memory controllers were designed so that every read was followed immediately by a write (because the read forced all bits to 0, and because the write assumed this had happened). [[Instruction set]]s were designed to take advantage of this.

For example, a value in memory could be read and modified almost as quickly as it could be read and written. In the [[PDP-6]], the <code>AOS*</code> (or <code>SOS*</code>) instructions incremented (or decremented) the value between the read phase and the write phase of a single memory cycle (perhaps signaling the memory controller to pause briefly in the middle of the cycle). This might be twice as fast as the process of obtaining the value with a read-write cycle, incrementing (or decrementing) the value in some processor register, and then writing the new value with another read-write cycle.

===Other forms of core memory===
[[File:Ferrite core memory.jpg|thumb|A 10.8&nbsp;× 10.8&nbsp;cm plane of magnetic core memory with 64&nbsp;× 64 bits (4&nbsp;Kb), as used in a [[CDC 6600]]. Inset shows ''word line'' architecture with two wires per bit]]

''Word line'' core memory was often used to provide register memory. Other names for this type are ''linear select'' and ''2-D''. This form of core memory typically wove three wires through each core on the plane, ''word read'', ''word write'', and ''bit sense/write''. To read or clear words, the full current is applied to one or more ''word read'' lines; this clears the selected cores and any that flip induce voltage pulses in their ''bit sense/write'' lines. For read, normally only one ''word read'' line would be selected; but for clear, multiple ''word read'' lines could be selected while the ''bit sense/write'' lines ignored. To write words, the half current is applied to one or more ''word write'' lines, and half current is applied to each ''bit sense/write'' line for a bit to be set. In some designs, the ''word read'' and ''word write'' lines were combined into a single wire, resulting in a memory array with just two wires per bit. For write, multiple ''word write'' lines could be selected. This offered a performance advantage over ''X/Y line coincident-current'' in that multiple words could be cleared or written with the same value in a single cycle. A typical machine's register set usually used only one small plane of this form of core memory. Some very large memories were built with this technology, for example the [[Extended Core Storage]] (ECS) auxiliary memory in the [[CDC 6600]], which was up to 2 million 60-bit words.

====Core rope memory====
{{Main articles|Core rope memory}}
[[Core rope memory]] is a [[read-only memory]] (ROM) form of core memory. In this case, the cores, which had more linear magnetic materials, were simply used as [[transformer]]s; no information was actually stored magnetically within the individual cores. Each bit of the word had one core. Reading the contents of a given memory address generated a pulse of current in a wire corresponding to that address. Each address wire was threaded either through a core to signify a binary [1], or around the outside of that core, to signify a binary [0]. As expected, the cores were much larger physically than those of read-write core memory. This type of memory was exceptionally reliable. An example was the [[Apollo Guidance Computer]] used for the [[NASA]] Moon landings.

===Physical characteristics===

====Speed====
The performance of early core memories can be characterized in today's terms as being very roughly comparable to a clock rate of 1&nbsp;[[MHz]] (equivalent to early 1980s home computers, like the [[Apple II]] and [[Commodore 64]]). Early core memory systems had cycle times of about 6&nbsp;[[μs]], which had fallen to 1.2&nbsp;μs by the early 1970s, and by the mid-70s it was down to 600&nbsp;[[nanosecond|ns]] (0.6&nbsp;μs). Some designs had substantially higher performance: the [[CDC 6600]] had a memory cycle time of 1.0&nbsp;μs in 1964, using cores that required a half-select current of 200 mA.<ref>{{cite book |title=Control Data 6600 Training Manual |section=Section 4 |date=June 1965 |publisher=Control Data Corporation |id=Document number 60147400}}</ref> Everything possible was done in order to decrease access times and increase data rates (bandwidth). To mitigate the often slow read times of core memory, read and write operations were often paralellized, with one word's worth of single-bit memory arrays set to work together so that a whole word's worth of memory could be read in a single memory access cycle.

====Reliability====
Core memory is [[non-volatile storage]]—it can retain its contents indefinitely without power. It is also relatively unaffected by [[electromagnetic pulse|EMP]] and radiation. These were important advantages for some applications like first-generation industrial [[programmable controllers]], military installations and vehicles like [[fighter aircraft]], as well as [[spacecraft]], and led to core being used for a number of years after availability of [[semiconductor]] MOS memory (see also [[MOSFET]]). For example, the [[Space Shuttle]] [[IBM System/4 Pi|IBM AP-101B]] flight computers used core memory, which preserved the contents of memory even through the ''[[Space Shuttle Challenger|Challenger]]''{{'}}s disintegration and subsequent plunge into the sea in 1986.<ref>{{cite web |url=http://www.magnet.fsu.edu/education/tutorials/museum/magneticcorememory.html |title=Magnetic Core Memory |publisher=National High Magnetic Field Laboratory: Museum of Electricity and Magnetism |location=US |archive-url=https://web.archive.org/web/20100610140932/http://www.magnet.fsu.edu/education/tutorials/museum/magneticcorememory.html |archive-date=10 June 2010 |url-status=dead}}</ref>

====Temperature sensitivity====
Another characteristic of early core was that the coercive force was very temperature-sensitive; the proper half-select current at one temperature is not the proper half-select current at another temperature. So a memory controller would include a temperature sensor (typically a [[thermistor]]) to adjust the current levels correctly for temperature changes. An example of this is the core memory used by [[Digital Equipment Corporation]] for their [[PDP-1]] computer; this strategy continued through all of the follow-on core memory systems built by [[Digital Equipment Corporation|DEC]] for their [[Programmed Data Processor|PDP]] line of air-cooled computers.

Another method of handling the temperature sensitivity was to enclose the magnetic core "stack" in a temperature-controlled oven. Examples of this are the heated-air core memory of the [[IBM 1620]] (which could take up to 30 minutes to reach [[operating temperature]], about {{convert|106|F}} and the heated-oil-bath core memory of the [[IBM 7090]], early [[IBM 7094]]s, and [[IBM 7030]]. Core was heated instead of cooled because the primary requirement was a ''consistent'' temperature, and it was easier (and cheaper) to maintain a constant temperature well above room temperature than one at or below it.

====Diagnosing====
Diagnosing hardware problems in core memory required time-consuming diagnostic programs to be run. While a quick test checked if every bit could contain a one and a zero, these diagnostics tested the core memory with worst-case patterns and had to run for several hours. As most computers had just a single core-memory board, these diagnostics also moved themselves around in memory, making it possible to test every bit. An advanced test was called a "[[Schmoo plot|Shmoo test]]" in which the half-select currents were modified along with the time at which the sense line was tested ("strobed"). The data plot of this test seemed to resemble a cartoon character called "[[Shmoo]]," and the name stuck. In many occasions, errors could be resolved by gently [[Percussive maintenance|tapping]] the printed circuit board with the core array on a table. This slightly changed the positions of the cores along the wires running through them, and could fix the problem. The procedure was seldom needed, as core memory proved to be very reliable compared to other computer components of the day.

<gallery widths="200px" heights="180px">
File:8 bytes vs. 8Gbytes.jpg|This [[microSDHC]] card holds 8 billion bytes (8 GB). It rests on a section of magnetic-core memory that uses 64 cores to hold eight bytes. The microSDHC card holds over one billion times more bytes in much less physical space.
File:Magnetic-core memory, 18x24 bits.jpg|Magnetic-core memory, 18×24 bits, with a [[US quarter]] for scale
File:Magnetic-core memory close-up.JPG|Magnetic-core memory close-up
File:Magnetic-core memory, at angle.jpg|At an angle
</gallery>