Editing Memory segmentation (section)

==Examples==

===[[Burroughs Large Systems|Burroughs large system architectures]]===
{{seealso|Burroughs large systems descriptors}}
Burroughs introduced segmentation on the [[B5000]], followed by the compatible B5500 and B5700.

The later [[B6500]] Replaced the Program reference table (PRT) with a [[Saguaro stack]], changed control word formats, changed [[Burroughs large systems descriptors|descriptor]] formats and changed the mechanism for referring to a control word or descriptor.

====B5000, B5500 and B5700====
{{see also|B5000 instruction set|Burroughs large systems descriptors#B5000, B5500 and B5700}}
Words in the [[Burroughs Large Systems#B5000, B5500, and B5700|B5000, B5500 and B5700]] are 48 bits long.<ref name=oper>{{Citation
 |     title = The Operational Characteristic of the Processors for the Burroughs B 5000
 |        id = 5000-21005A
 |   edition = A 
 |      year = 1962
 |       url = https://bitsavers.org/pdf/burroughs/LargeSystems/B5000_5500_5700/5000-21005_B5000_operChar_1963.pdf
 |  location = Detroit
 | publisher = Burroughs
 }}
</ref> [[Burroughs large systems descriptors|Descriptors]] have the uppermost bit set in the word. They reside in either the Program Reference Table (PRT) or the stack, and contain a ''presence bit'' indicating whether the data are present in memory. There are distinct data and program descriptors.<ref name=oper />{{rp|pages = 4{{hyp}}2-4{{hyp}}4}}

====B6500, B7500 and successors====
{{see also|Burroughs B6x00-7x00 instruction set|Burroughs large systems descriptors#B6500, B7500 and successors}}
Words in the B6500 and its successors have 48 bits of data and 3 tag bits.<!--4 bits in later machines?--><ref name="b6500-ref-man">{{cite book |url=http://www.bitsavers.org/pdf/burroughs/LargeSystems/B6500_6700/1043676_B6500_RefMan_Sep69.pdf |title=B6500 Information Processing Systems Reference Manual |publisher=Burroughs |date=September 1969}}</ref>{{rp|page=2{{hyp}}1}} The tag bits indicate the type of data contained in the word; there are several descriptor types, indicated by different tag bit values.<ref name="b6500-ref-man" />{{rp|pages=6{{hyp}}5-6{{hyp}}10}} Control words and descriptors reside in the Saguaro stack. Array segments may be paged.

The line includes the B6500, B6700, B7700, B6800, B6900, B5900, the A-series Burroughs and Unisys machines, and the current Clearpath MCP systems (Libra). While there have been a few enhancements over the years, particularly hardware advances, the architecture has changed little. The segmentation scheme has remained the same, see [[Virtual Memory#Segmented_virtual_memory|Segmented memory]].

===Multics architectures===
{{stub-section|date=January 2024}}

===S/370 architecture===
In the [[IBM System/370]] models{{efn|Models 115, 125, 135, 138, 145, 148, 155 II, 158, 165 II, and 168}} with virtual storage<ref name="S370">{{cite book
|title=IBM System/370 Principles of Operation
|id=GA22-7000-4
|edition=Fourth
|date=September 1974
|pages=57–68
|series=Systems
|publisher=[[IBM]]
|section=Dynamic Address Translation
|section-url=http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf#page=57
|url=http://www.bitsavers.org/pdf/ibm/370/princOps/GA22-7000-4_370_Principles_Of_Operation_Sep75.pdf
}}
<!-- This is the most recent version that I could find in bitsavers -->
</ref><ref name="S370-10">{{cite book
|title=IBM System/370 Principles of Operation
|id=GA22-7000-10
|edition=Eleventh
|date=September 1987
|section=Dynamic Address Translation
|pages=3-20-3-38
|publisher=IBM
}}
</ref> (DAT) and 24-bit addresses, [[control register]] 0 specifies a segment size of either 64 KiB or 1 MiB and a page size of either 2 KiB or 4 KiB; control register 1 contains a Segment Table Designator (STD), which specifies the length and real address of the segment table. Each segment table entry contains a page table location, a page table length and an invalid bit. IBM later expanded the address size to 31 bits and added two bits to the segment table entries:

;Segment-protection bit
:Segment is read-only
;Common-segment bit
:The segment is shared between address spaces; this bit is set to optimize TLB use

Each of IBM's DAT implementations includes a translation cache, which IBM called a Translation Lookaside Buffer (TLB). While Principles of Operation discusses the TLB in general terms, the details are not part of the architecture and vary from model to model.

Starting with the [[IBM 303X|3031, 3032, and 3033]] processor complexes, IBM offered a feature called ''Dual-address Space''<ref name="S370-10"/>{{rp|at=Dual-Address-Space Control|pp=5-13-5-17}}{{rp|at=DAS Authorization Mechanisms|pp=5-17-5-20}}{{rp|at=PC-Number Translation|pp=5-21-5-24}}<ref name="S370-XA">{{cite book
|title=IBM System/370 Extended Architecture Principles of Operation
|id=SA22-7085-1
|edition=Second
|date=January 1987
|pages=3-13-3-14
|publisher=IBM
|section=Address spaces
|section-url=http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf#page=40
|url=http://bitsavers.org/pdf/ibm/370/princOps/SA22-7085-1_370-XA_Principles_of_Operation_Jan87.pdf
}}
</ref> (DAS), which allows a program to switch between the translation tables for two address spaces, referred to as ''primary address space'' (CR1) and ''secondary address space'' (CR7), and to move data between the address spaces subject to protection key. DAS supports a translation table to convert a 16-bit address space number (ASN) to an STD, with privileged instructions to load the STD into CR1 (primary) or CR7 (secondary).

===x86 architecture===
{{Main|x86 memory segmentation}}
Early [[x86]] processors, beginning with the [[Intel 8086]], provide crude memory segmentation and no [[memory protection]]. (Every byte of every segment is always available to any program.) The 16-bit segment registers allow for 65,536 segments; each segment begins at a fixed offset equal to 16 times the segment number; the segment starting address granularity is 16 bytes. Each segment grants read-write access to 64&nbsp;KiB (65,536 bytes) of address space (this limit is set by the 16-bit PC and SP registers; the processor does no bounds checking). Offset+address exceeding 0xFFFFF wraps around to 0x00000. Each 64&nbsp;KiB segment overlaps the next 4,095 segments; each physical address can be denoted by 4,096 segment–offset pairs. This scheme can address only 1&nbsp;MiB (1024&nbsp;KiB) of physical memory (and memory-mapped i/o). (Optional [[expanded memory]] hardware can add bank-switched memory under software control.) Intel retroactively named the sole operating mode of these x86 CPU models "[[real mode]]".

The [[Intel 80286]] and later processors add "286 [[protected mode]]", which retains 16-bit addressing, and adds segmentation (without paging) and per-segment memory protection. For backward compatibility, all x86 CPUs start up in "real mode", with the same fixed overlapping 64&nbsp;KiB segments, no memory protection, only 1&nbsp;MiB physical address space, and some subtle differences ([[high memory area]], [[unreal mode]]). In order to use its full 24-bit (16&nbsp;MiB) physical address space and advanced [[memory management unit|MMU]] features, an 80286 or later processor must be switched into "protected mode" by software, usually the operating system or a [[DOS extender]]. If a program does not use the segment registers, or only puts values into them that it receives from the operating system, then identical code can run in real mode or protected mode, but most real-mode software computes new values for the segment registers, breaking this compatibility.

The [[Intel i386]] and later processors add "386 [[protected mode]]", which uses 32-bit addressing, retains segmentation, and adds [[memory paging]]. In these processors, the segment table, rather than pointing to a page table for the segment, contains the segment address in ''linear memory''. When paging is enabled, addresses in linear memory are then mapped to physical addresses using a separate page table. Most operating systems did not use the segmentation capability, opting to keep the base address in all segment registers equal to 0 at all times and provide per-page memory protection and swapping using only paging.  Some use the CS register to provide [[executable space protection]] on processors lacking the [[NX bit]] or use the FS or GS registers to access thread-local storage.<ref name="pietrek-windows-nt">{{cite web |url=https://learn.microsoft.com/en-us/archive/msdn-magazine/2006/may/x64-starting-out-in-64-bit-windows-systems-with-visual-c |title=Everything You Need To Know To Start Programming 64-Bit Windows Systems |publisher=Microsoft |author=Matt Pietrek |author-link=Matt Pietrek |date=May 2006 |access-date=April 18, 2023}}</ref><ref name="drepper-linux-etc">{{cite web |url=http://www.akkadia.org/drepper/tls.pdf |title=ELF Handling For Thread-Local Storage |first=Ulrich |last=Drepper |date=August 22, 2013}}</ref>

The [[x86-64]] architecture does not support segmentation in "[[long mode]]" (64-bit mode).<ref name=":1">{{cite book |title=AMD64 Technology AMD64 Architecture Programmer's Manual Volume 2: System Programming |publisher=Advanced Micro Devices |volume=2 |date=2018 |url=https://www.amd.com/system/files/TechDocs/24594.pdf}}</ref> Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 2<sup>64</sup>. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes such as thread-local storage.<ref name="pietrek-windows-nt" /><ref name="drepper-linux-etc" />