Editing National Semiconductor SC/MP (section)

===Bus control===
[[File:National Semiconductor SC-MP Development System.jpg|thumb|National Semiconductor SC/MP Development System]]
A feature of the SC/MP was a shared daisy-chained control line that allowed multiple SC/MP, or more commonly a single SC/MP and related [[direct memory access]] (DMA) controllers, to share access to a single [[main memory]]. When any one of the chips on the bus desired access to memory, it would set the ENOUT pin high, thereby signalling the other chip's ENIN pins that they had to release the bus. With most other processors, this would normally require external logic implemented by the board designers to pause the CPU to the same end, often with some complexity due to the internal instruction timing that was not visible to the external circuits. In the SC/MP this was all included internally so a single line on the circuit board was all that was needed to implement this feature.{{sfn|Handbook|1977|p=2C3-1}}

The original idea was to ease the creation of [[microcontroller]]-like applications containing an SC/MP, one or more DMA controllers, and a single shared memory. Designed specifically to be as low-cost as possible in terms of an overall system, the desire to lower the cost of the SC/MP itself also led to decisions about the bit-serial ALU and the inclusion of serial input/output lines to eliminate the need for a separate [[UART]] (this feature was removed in the later SC/MP III).{{sfn|Handbook|1977|p=2C1-12}} Osborne's review of the system stated it was the "microprocessor of choice in any multi-processor application"{{sfn|Osborne|Kane|1981|p=3.1}} but this market seems to have been limited as sales were never particularly strong.