Editing PCI-X (section)

==Technical description==
PCI-X revised the [[conventional PCI]] standard by doubling the maximum clock speed (from 66&nbsp;MHz to 133&nbsp;MHz)<ref name="PCI-SIG" /> and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to [[64-bit computing|64 bits]] at 66&nbsp;MHz (though anything above 32&nbsp;bits at 33&nbsp;MHz is seen only in high-end systems). The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06&nbsp;GB/s, compared to 133&nbsp;MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI, allowing, for example, faulty cards to be reinitialized or taken offline.

PCI-X is backward compatible to PCI in the sense that the entire bus falls back to PCI if any card on the bus does not support PCI-X.

The two most fundamental changes are:
* The shortest time between a signal appearing on the PCI bus and a response to that signal occurring on the bus has been extended to 2 cycles, rather than 1. This allows much faster clock rates, but causes many protocol changes:
** The ability of the conventional PCI bus protocol to insert wait states on any cycle based on the IRDY# and TRDY# signals has been deleted; PCI-X only allows bursts to be interrupted at 128-byte boundaries.
** The initiator must deassert FRAME# ''two'' cycles before the end of the transaction.
** The initiator may not insert wait states. The target may, but only before any data is transferred, and wait states for writes are limited to multiples of 2 clock cycles.
** Likewise, the length of a burst is decided before it begins; it may not be halted on an arbitrary cycle using the FRAME# and STOP# signals.
** Subtractive decode DEVSEL# takes place two cycles after the "slow DEVSEL#" cycle rather than on the next cycle.
* After the address phase (and before any device has responded with DEVSEL#), there is an additional 1-cycle "attribute phase", during which 36 additional bits (both AD and C/BE# lines are used) of information about the operation are transmitted. These include 16&nbsp;bits of requester identification (PCI bus, device and function number), 12 bits of burst length, 5 bits of tag (for associating split transactions), and 3&nbsp;bits of additional status.