Editing PCI Express (section)

== Form factors ==

=== PCI Express (standard) <span class="anchor" id="HHHL"></span><span class="anchor" id="FHHL"></span> ===
[[File:Intel P3608 NVMe flash SSD, PCI-E add-in card.jpg|thumb|Intel P3608 NVMe flash SSD, PCIe add-in card|alt=]]A PCI Express card fits into a slot of its physical size or larger (with x16 as the largest used), but may not fit into a smaller PCI Express slot; for example, a x16 card may not fit into a x4 or x8 slot. Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical and logical connection.

The number of lanes actually connected to a slot may also be fewer than the number supported by the physical slot size. An example is a x16 slot that runs at x4, which accepts any x1, x2, x4, x8 or x16 card, but provides only four lanes. Its specification may read as "x16 (x4 mode)", while "mechanical @ electrical" notation (e.g. "x16&nbsp;@&nbsp;x4") is also common.{{Citation needed|date=July 2022}} The advantage is that such slots can accommodate a larger range of PCI Express cards without requiring motherboard hardware to support the full transfer rate. Standard mechanical sizes are x1, x4, x8, and x16. Cards using a number of lanes other than the standard mechanical sizes need to physically fit the next larger mechanical size (e.g. an x2 card uses the x4 size, or an x12 card uses the x16 size).

The cards themselves are designed and manufactured in various sizes. For example, [[solid-state drive]]s (SSDs) that come in the form of PCI Express cards often use [[Conventional PCI#Low-profile cards|HHHL]] (half height, half length) and [[Conventional PCI#Half-length full-height card|FHHL]] (full height, half length) to describe the physical dimensions of the card.<ref name="8AKZj" /><ref name="c1yve" />

{| class="wikitable"
|-
! rowspan=2" | PCI card type
! colspan="2" | Dimensions height × length × width, maximum
|-
! (mm)
! (in)
|-
| Full-Length
| 111.15 × 312.00 × 20.32
| 4.376 × 12.283 × 0.8
|-
| Half-Length
| 111.15 × 167.65 × 20.32
| 4.376 × {{0}}6.600 × 0.8
|-
| Low-Profile/Slim
| {{0}}68.90 × 167.65 × 20.32
| 2.731 × {{0}}6.600 × 0.8
|}

==== Non-standard video card form factors ====
Modern (since {{circa|2012}}<ref name="j6TTS" />) gaming [[video card]]s usually exceed the height as well as thickness specified in the PCI Express standard, due to the need for more capable and quieter [[Computer fan|cooling fans]], as gaming video cards often emit hundreds of watts of heat.<ref name="RAreG" /> Modern computer cases are often wider to accommodate these taller cards, but not always. Since full-length cards (312&nbsp;mm) are uncommon, modern cases sometimes cannot accommodate them. The thickness of these cards also typically occupies the space of 2 to 5<ref>{{Cite web |last=Discuss |first=btarunr |date=2023-01-06 |title=ASUS x Noctua RTX 4080 Graphics Card is 5 Slots Thick, We Go Hands-on |url=https://www.techpowerup.com/303148/asus-x-noctua-rtx-4080-graphics-card-is-5-slots-thick-we-go-hands-on |access-date=2024-09-19 |website=TechPowerUp |language=en}}</ref> PCIe slots. In fact, even the methodology of how to measure the cards varies between vendors, with some including the metal bracket size in dimensions and others not.

For instance, comparing three high-end video cards released in 2020: a [[Sapphire Technology|Sapphire]] [[Radeon RX 5000 series|Radeon RX 5700 XT]] card measures 135&nbsp;mm in height (excluding the metal bracket), which exceeds the PCIe standard height by 28&nbsp;mm,<ref name="E0Tsg" /> another Radeon RX 5700 XT card by [[XFX]] measures 55&nbsp;mm thick (i.e. 2.7 PCI slots at 20.32&nbsp;mm), taking up 3 PCIe slots,<ref name="mAt96" /> while an [[Asus]] [[GeForce 30 series|GeForce RTX 3080]] video card takes up two slots and measures 140.1{{nbsp}}mm × 318.5{{nbsp}}mm × 57.8{{nbsp}}mm, exceeding PCI Express's maximum height, length, and thickness respectively.<ref name="kk3xz" />

==== Pinout ====
The following table identifies the conductors on each side of the [[edge connector]] on a PCI Express card. The solder side of the [[printed circuit board]] (PCB) is the A-side, and the component side is the B-side.<ref name="IM1RH" /> PRSNT1# and PRSNT2# pins must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted. The WAKE# pin uses full voltage to wake the computer, but must be [[pull up resistor|pulled high]] from the standby power to indicate that the card is wake capable.<ref name="PCIe card 2" />

{| class="wikitable"
|+ PCI Express connector pinout (x1, x4, x8 and x16 variants)
! Pin !! Side B !! Side A !! Description
| rowspan=54 |
! Pin !! Side B !! Side A !! Description
|-
! {{0}}1
|style="background:silver"| +12&nbsp;V || style="background:#9f9"| PRSNT1# ||align="left"| Must connect to farthest PRSNT2# pin
! 50
|style="background:#99f"| HSOp(8) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 8 transmit data, + and −
|-
! {{0}}2
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V || rowspan="2" style="text-align:left;"|Main power pins
! 51
|style="background:#99f"| HSOn(8) ||style="background:#999"| Ground
|-
! {{0}}3
|style="background:silver"| +12&nbsp;V ||style="background:silver"| +12&nbsp;V
! 52
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(8) || rowspan="2" style="text-align:left;"| Lane 8 receive data, + and −
|-
! {{0}}4
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 53
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(8)
|-
! {{0}}5
|style="background:#fc6"| SMCLK ||style="background:#99f"| TCK || rowspan="5" style="text-align:left;"| [[SMBus]] and [[JTAG]] port pins
! 54
|style="background:#99f"| HSOp(9) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 9 transmit data, + and −
|-
! {{0}}6
|style="background:#fc6"| SMDAT ||style="background:#99f"| TDI
! 55
|style="background:#99f"| HSOn(9) ||style="background:#999"| Ground
|-
! {{0}}7
|style="background:#999"| Ground ||style="background:#f9f"| TDO
! 56
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(9) || rowspan="2" style="text-align:left;"| Lane 9 receive data, + and −
|-
! {{0}}8
|style="background:silver"| +3.3&nbsp;V ||style="background:#99f"| TMS
! 57
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(9)
|-
! {{0}}9
|style="background:#99f"| TRST# ||style="background:silver"| +3.3&nbsp;V
! 58
|style="background:#99f"| HSOp(10) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 10 transmit data, + and −
|-
! 10
|style="background:silver"|+3.3&nbsp;V aux ||style="background:silver"| +3.3&nbsp;V ||align="left"| Aux power & [[Standby power]]
! 59
|style="background:#99f"| HSOn(10) ||style="background:#999"| Ground
|-
! 11
|style="background:#fc6"| WAKE# ||style="background:#fc6"| PERST# ||align="left"| Link reactivation; fundamental reset <ref name="ajnim" />
! 60
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(10) || rowspan="2" style="text-align:left;"| Lane 10 receive data, + and −
|-
!colspan=4| Key notch
! 61
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(10)
|-
! 12
|style="background:#f9f"| CLKREQ#<ref name="vj2hg" /> ||style="background:#999"| Ground ||align="left"| Clock Request Signal
! 62
|style="background:#99f"| HSOp(11) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 11 transmit data, + and −
|-
! 13
|style="background:#999"| Ground ||style="background:#99f"| REFCLK+ ||align="left"| Reference clock differential pair
! 63
|style="background:#99f"| HSOn(11) ||style="background:#999"| Ground
|-
! 14
|style="background:#99f"| HSOp(0) ||style="background:#99f"| REFCLK− || rowspan="2" style="text-align:left;"| Lane 0 transmit data, + and −
! 64
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(11) || rowspan="2" style="text-align:left;"| Lane 11 receive data, + and −
|-
! 15
|style="background:#99f"| HSOn(0) ||style="background:#999"| Ground
! 65
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(11)
|-
! 16
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(0) || rowspan="2" style="text-align:left;"| Lane 0 receive data, + and −
! 66
|style="background:#99f"| HSOp(12) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 12 transmit data, + and −
|-
! 17
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(0)
! 67
|style="background:#99f"| HSOn(12) ||style="background:#999"| Ground
|-
! 18
|style="background:#999"| Ground ||style="background:#999"| Ground ||
! 68
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(12) || rowspan="2" style="text-align:left;"| Lane 12 receive data, + and −
|-
|colspan=4| PCI Express x1 cards end at pin 18
! 69
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(12)
|-
! 19
|style="background:#99f"| HSOp(1) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 1 transmit data, + and −
! 70
|style="background:#99f"| HSOp(13) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 13 transmit data, + and −
|-
! 20
|style="background:#99f"| HSOn(1) ||style="background:#999"| Ground
! 71
|style="background:#99f"| HSOn(13) ||style="background:#999"| Ground
|-
! 21
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(1) || rowspan="2" style="text-align:left;"| Lane 1 receive data, + and −
! 72
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(13) || rowspan="2" style="text-align:left;"| Lane 13 receive data, + and −
|-
! 22
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(1)
! 73
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(13)
|-
! 23
|style="background:#99f"| HSOp(2) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 2 transmit data, + and −
! 74
|style="background:#99f"| HSOp(14) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 14 transmit data, + and −
|-
! 24
|style="background:#99f"| HSOn(2) ||style="background:#999"| Ground
! 75
|style="background:#99f"| HSOn(14) ||style="background:#999"| Ground
|-
! 25
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(2) || rowspan="2" style="text-align:left;"| Lane 2 receive data, + and −
! 76
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(14) || rowspan="2" style="text-align:left;"| Lane 14 receive data, + and −
|-
! 26
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(2)
! 77
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(14)
|-
! 27
|style="background:#99f"| HSOp(3) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 3 transmit data, + and −
! 78
|style="background:#99f"| HSOp(15) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 15 transmit data, + and −
|-
! 28
|style="background:#99f"| HSOn(3) ||style="background:#999"| Ground
! 79
|style="background:#99f"| HSOn(15) ||style="background:#999"| Ground
|-
! 29
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(3) || rowspan="2" style="text-align:left;"| Lane 3 receive data, + and −<br />"Power brake", active-low to reduce device power
! 80
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(15) || rowspan="2" style="text-align:left;"| Lane 15 receive data, + and −
|-
! 30
|style="background:#fc6"| PWRBRK#<ref name="YpQVq" /> ||style="background:#f9f"| HSIn(3)
! 81
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(15)
|-
! 31
|style="background:#9f9"| PRSNT2# ||style="background:#999"| Ground ||rowspan=2|
! 82
|style="background:#ff9"| Reserved ||style="background:#999"| Ground ||
|-
! 32
|style="background:#999"| Ground ||style="background:#ff9"| Reserved
|-
|colspan=4| PCI Express x4 cards end at pin 32
|-
! 33
|style="background:#99f"| HSOp(4) ||style="background:#ff9"| Reserved || rowspan="2" style="text-align:left;"| Lane 4 transmit data, + and −
|-
! 34
|style="background:#99f"| HSOn(4) ||style="background:#999"| Ground
|-
! 35
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(4) || rowspan="2" style="text-align:left;"| Lane 4 receive data, + and −
|-
! 36
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(4)
|-
! 37
|style="background:#99f"| HSOp(5) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 5 transmit data, + and −
|-
! 38
|style="background:#99f"| HSOn(5) ||style="background:#999"| Ground
|-
! 39
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(5) || rowspan="2" style="text-align:left;"| Lane 5 receive data, + and −
|-
! 40
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(5)
|-
! 41
|style="background:#99f"| HSOp(6) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 6 transmit data, + and −
|-
! 42
|style="background:#99f"| HSOn(6) ||style="background:#999"| Ground
|-
! 43
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(6) || rowspan="2" style="text-align:left;"| Lane 6 receive data, + and −
!colspan=4| Legend
|-
! 44
|style="background:#999"| Ground ||style="background:#f9f"| HSIn(6)
!style="background:#999" colspan=2| Ground pin
| colspan="2" style="text-align:left;"| Zero volt reference
|-
! 45
|style="background:#99f"| HSOp(7) ||style="background:#999"| Ground || rowspan="2" style="text-align:left;"| Lane 7 transmit data, + and −
!style="background:silver" colspan=2| Power pin
| colspan="2" style="text-align:left;"| Supplies power to the PCIe card
|-
! 46
|style="background:#99f"| HSOn(7) ||style="background:#999"| Ground
!style="background:#f9f" colspan=2| Card-to-host pin
| colspan="2" style="text-align:left;"| Signal from the card to the motherboard
|-
! 47
|style="background:#999"| Ground ||style="background:#f9f"| HSIp(7) || rowspan="2" style="text-align:left;"| Lane 7 receive data, + and −
!style="background:#99f" colspan=2| Host-to-card pin
| colspan="2" style="text-align:left;"| Signal from the motherboard to the card
|-
! 48
|style="background:#9f9"| PRSNT2# ||style="background:#f9f"| HSIn(7)
!style="background:#fc6" colspan=2| [[Open drain]]
| colspan="2" style="text-align:left;"| May be pulled low or sensed by multiple cards
|-
! 49
|style="background:#999"| Ground ||style="background:#999"| Ground ||
!style="background:#9f9" colspan=2| Sense pin
| colspan="2" style="text-align:left;"| Tied together on card
|-
|colspan=4| PCI Express x8 cards end at pin 49
!style="background:#ff9" colspan=2| Reserved
| colspan="2" style="text-align:left;"| Not presently used, do not connect
|}

==== Power ====
[[File:Powering of PCIe Slot.png|thumb|upright=1.25|The main {{val|12|ul=V}} power supply for the PCIe slot is pins B2, B3 (side B) and pins A2, A3 (side A). Power standby {{val|3.3|ul=V}} is pin B10 and A10. PCIe x1 cards can draw up to {{val|25|ul=W}} and x16 graphics cards can draw up to {{val|75|ul=W}}, combined.<ref>{{cite web |date=2022-01-16 |title=Where Does PCIe Cable Go? |url=https://greatpcreview.com/guides/where-does-pcie-cables-go/ |access-date=2022-06-10 |language=en-US}}</ref>]]

===== Slot power =====
<!--
Please DO NOT add the claim that the PCI express 2.x standard adds support for up to 150&nbsp;W from the slot itself without a very good reference. While several references make the claim, particularly around the time of release, other references particularly those relying on the spec. dispute this. See the talk page discussion dated November 2012 for details.
-->
All PCI express cards may consume up to {{val|3|ul=A}} at {{val|+3.3|ul=V}} ({{val|9.9|ul=W}}). The amount of +12&nbsp;V and total power they may consume depends on the form factor and the role of the card:<ref name="CEM1.1" />{{rp|35–36}}<ref name="jArAO" /><ref>''PCI Express Base Specification, Revision 1.1'' Page 332</ref>
* x1 cards are limited to 0.5&nbsp;A at +12{{nbsp}}V (6&nbsp;W) and 10&nbsp;W combined.
* x4 and wider cards are limited to 2.1&nbsp;A at +12{{nbsp}}V (25&nbsp;W) and 25&nbsp;W combined.
* A full-sized x1 card may draw up to the 25&nbsp;W limits after initialization and software configuration as a high-power device.
* A full-sized x16 graphics card may draw up to 5.5&nbsp;A at +12{{nbsp}}V (66&nbsp;W) and 75&nbsp;W combined after initialization and software configuration as a high-power device.<ref name="PCIe card 2" />{{rp|38–39}}

===== 6- and 8-pin power connectors =====
[[File:PCI Express Power Supply Connector-female PNr°0438.jpg|thumb|upright=1.25|8-pin (left) and 6-pin (right) [[Molex Mini-fit Jr.|power connectors]] used on PCI Express cards]]

Optional connectors add {{val|75|ul=W}} (6-pin) or {{val|150|ul=W}} (8-pin) of +12&nbsp;V power for up to {{val|300|ul=W}} total ({{nowrap|2 @ 75&nbsp;W + 1 @ 150&nbsp;W}}).
* Sense0 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.
* Sense1 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.

Some cards use two 8-pin connectors, but that has not been standardized {{as of|lc=y|2018}}. Therefore, such cards must not carry the official PCI Express logo. This configuration allows 375&nbsp;W total ({{nowrap|1 @ 75&nbsp;W + 2 @ 150&nbsp;W}}) and will likely be standardized by PCI-SIG with the PCI Express 4.0 standard.{{Update inline|reason=PCI Express is at 5.0 already…|date=May 2021}} The 8-pin PCI Express connector should not be confused with the [[EPS12V]] connector, which is mainly used for powering SMP and multi-core systems. The power connectors are variants of the Molex Mini-Fit Jr. series connectors.<ref name="JuErgh" />
{| class="wikitable" style="background:white; border:0"
|+ Molex Mini-Fit Jr. part numbers<ref name="JuErgh" />
! Pins
! Female/receptacle <br />on PS cable
!Male/right-angle <br />header on PCB
|-
|6-pin
|45559-0002
|45558-0003
|-
|8-pin
|45587-0004
|45586-0005, 45586-0006
|}
{| class="wikitable" style="border:0"
! colspan=2 style="background:white; border:0" | 6-pin power connector (75&nbsp;W)<ref name="o2GFI" />
| rowspan=10 style="border:0; background:white"|
! colspan=2 style="background:white; border:0" | 8-pin power connector (150&nbsp;W)<ref name="uLc7Q" /><ref name="CEM3.0" /><ref name="mcd6L" />
| rowspan=10 style="border:0;background:white"| [[File:PCIe6connector.svg|thumb|185px|<small>6 pin power connector pin map</small>]]<br />
                               [[File:PCIe8connector.svg|thumb|224px|&emsp;&emsp;<small>8 pin power connector pin map</small>]]
|-
! Pin !! Description
! Pin !! Description
|-
| {{0}}1 || +12&nbsp;V
| {{0}}1 || +12&nbsp;V
|-
| {{0}}2 || {{n/a|Not connected (usually +12&nbsp;V as well)}}
| {{0}}2 || +12&nbsp;V
|-
| {{0}}3 || +12&nbsp;V
| {{0}}3 || +12&nbsp;V
|-
| colspan=2 style="background:white; border:0" |
| {{0}}4 || Sense1 (8-pin connected{{efn-ua|When a 6-pin connector is plugged into an 8-pin receptacle the card is notified by a missing ''Sense1'' that it may only use up to 75&nbsp;W.}})
|-
| {{0}}4 || Ground
| {{0}}5 || Ground
|-
| {{0}}5 || Sense
| {{0}}6 || Sense 0 (6-pin or 8-pin connected)
|-
| {{0}}6 || Ground
| {{0}}7 || Ground
|-
| colspan=2 style="background:white; border:0" |
| {{0}}8 || Ground
|}
{{notelist-ua}}

===== 12VHPWR connector =====
{{Excerpt|16-Pin 12vHPWR connector|templates=-Advert}}

===== 48VHPWR connector =====
In 2023 PCIe CEM 5.1 introduced a connector for 48 Volts with two current-carrying contacts and four sense pins.<ref name="PCIe5.1 CEM">''PCI Express Card Electromechanical Specification Revision 5.1, Version 1.0'', 30 March 2023 – 10. PCI Express 48VHPWR Auxiliary Power Connector Definition</ref> The contacts are rated for 15 Amps continuous current. The 48VHPWR connector can carry 720 watts. Later it was removed and an incompatible 48V 1x2 connector was introduced where Sense0 and Sense1 are located farthest from each other.
	
{| class="wikitable"
|+ 48VHPWR pinout
! Pin !! Signal
|-
| P1 || +48 V
|-
|P2 || Ground
|-
| S1 || CARD_PWR_STABLE
|-
| S2 || CARD_CBL_PRES#
|-
| S3 || SENSE0
|-
| S4 || SENSE1
|}

=== PCI Express Mini Card <span class="anchor" id="MINI-CARD"></span> ===
<!-- [[PCI Express Mini Card]], [[Mini PCI Express]], [[Mini PCIe]], [[Mini PCI-E]], and [[M-PCIe]] redirect here. -->
[[File:Intel WM3945ABG MOW2 and its connector 20070216.jpg|thumb|A [[WLAN]] PCI Express Mini Card and its connector]]
[[File:MiniPCI and MiniPCI Express cards.jpg|thumb|MiniPCI and MiniPCI Express cards in comparison]]

'''PCI Express Mini Card''' (also known as '''Mini PCI Express''', '''Mini PCIe''', '''Mini PCI-E''', '''mPCIe''', and '''PEM'''), based on PCI Express, is a replacement for the [[Mini PCI]] form factor. It is developed by the [[PCI-SIG]]. The host device supports both PCI Express and [[USB]]&nbsp;2.0 connectivity, and each card may use either standard. Most laptop computers built after 2005 use PCI Express for expansion cards; however, {{as of|2015|lc=yes}}, many vendors are moving toward using the newer [[M.2]] form factor for this purpose.<ref>{{cite web | url=https://arstechnica.com/gadgets/2015/02/understanding-m-2-the-interface-that-will-speed-up-your-next-ssd/ | title=Understanding M.2, the interface that will speed up your next SSD | date=8 February 2015 }}</ref>

Due to different dimensions, PCI Express Mini Cards are not physically compatible with standard full-size PCI Express slots; however, passive adapters exist that let them be used in full-size slots.<ref name="DmwJz" /> 

==== Physical dimensions ====
Dimensions of PCI Express Mini Cards are 30&nbsp;mm × 50.95&nbsp;mm (width&nbsp;× length) for a Full Mini Card. There is a 52-pin [[edge connector]], consisting of two staggered rows on a 0.8&nbsp;mm pitch. Each row has eight contacts, a gap equivalent to four contacts, then a further 18 contacts. [[Printed circuit board|Boards]] have a thickness of 1.0&nbsp;mm, excluding the components. A "Half Mini Card" (sometimes abbreviated as HMC) is also specified, having approximately half the physical length of 26.8&nbsp;mm. There are also half size mini PCIe cards that are 30 x 31.90 mm which is about half the length of a full size mini PCIe card.<ref>{{cite book | url=https://books.google.com/books?id=otfPEAAAQBAJ&dq=pci+express+micro&pg=PT628 | isbn=978-0-13-816625-0 | title=IT Essentials Companion Guide v8 | date=9 July 2023 | publisher=Cisco Press }}</ref><ref>{{cite book | url=https://google.com.pa/books/edition/Mobile_Computing_Deployment_and_Manageme/rP5gBgAAQBAJ?hl=en&gbpv=1&dq=mini+pcie+full+size+half+size&pg=PA491&printsec=frontcover | isbn=978-1-118-82461-0 | title=Mobile Computing Deployment and Management: Real World Skills for CompTIA Mobility+ Certification and Beyond | date=24 February 2015 | publisher=John Wiley & Sons }}</ref> 

==== Electrical interface ====
PCI Express Mini Card edge connectors provide multiple connections and buses:
* PCI Express x1 (with SMBus)
* USB&nbsp;2.0
* Wires to diagnostics LEDs for wireless network (i.e., [[Wi-Fi]]) status on computer's chassis
* [[Subscriber Identity Module|SIM]] card for [[GSM]] and [[WCDMA]] applications (UIM signals on spec.)
* Future extension for another PCIe lane
* 1.5&nbsp;V and 3.3&nbsp;V power

==== Mini-SATA (mSATA) variant <span class="anchor" id="MSATA"></span> ====
[[File:Intel 525 mSATA SSD.jpg|thumb|upright|An Intel mSATA SSD]]
Despite sharing the Mini PCI Express form factor, an [[mSATA]] slot is not necessarily electrically compatible with Mini PCI Express. For this reason, only certain notebooks are compatible with mSATA drives. Most compatible systems are based on Intel's Sandy Bridge processor architecture, using the Huron River platform. Notebooks such as Lenovo's ThinkPad T, W and X series, released in March–April 2011, have support for an mSATA SSD card in their [[Wireless WAN|WWAN]] card slot. The ThinkPad Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560/Y570/Y580 also support mSATA.<ref name="5xxpo" /> On the contrary, the L-series among others can only support M.2 cards using the PCIe standard in the WWAN slot.

Some notebooks (notably the [[Asus Eee PC]], the [[Apple Inc.|Apple]] [[MacBook Air]], and the Dell mini9 and mini10) use a variant of the PCI Express Mini Card as an [[solid-state drive|SSD]]. This variant uses the reserved and several non-reserved pins to implement SATA and IDE interface passthrough, keeping only USB, ground lines, and sometimes the core PCIe x1 bus intact.<ref name="EeePC" /> This makes the "miniPCIe" flash and solid-state drives sold for netbooks largely incompatible with true PCI Express Mini implementations.

Also, the typical Asus miniPCIe SSD is 71&nbsp;mm long, causing the Dell 51&nbsp;mm model to often be (incorrectly) referred to as half length. A true 51&nbsp;mm Mini PCIe SSD was announced in 2009, with two stacked PCB layers that allow for higher storage capacity. The announced design preserves the PCIe interface, making it compatible with the standard mini PCIe slot. No working product has yet been developed.

Intel has numerous desktop boards with the PCIe x1 Mini-Card slot that typically do not support mSATA SSD. A list of desktop boards that natively support mSATA in the PCIe x1 Mini-Card slot (typically multiplexed with a SATA port) is provided on the Intel Support site.<ref name="xpI66" />

=== PCI Express M.2 ===
{{Main|M.2}}
M.2 replaces the mSATA standard and Mini PCIe.<ref name="oL68r" /> Computer bus interfaces provided through the M.2 connector are PCI Express 3.0 or higher (up to four lanes), Serial ATA 3.0, and USB 3.0 (a single logical port for each of the latter two). It is up to the manufacturer of the M.2 host or device to choose which interfaces to support, depending on the desired level of host support and device type.

=== PCI Express External Cabling <span class="anchor" id="EXTERNAL-CABLING"></span> ===
''PCI Express External Cabling'' (also known as ''External PCI Express'', ''Cabled PCI Express'', or ''ePCIe'') specifications were released by the [[PCI-SIG]] in February 2007.<ref name="pcie_cabling1.0" /><ref name="ZTXPi" />

Standard cables and connectors have been defined for x1, x4, x8, and x16 link widths, with a transfer rate of 250&nbsp;MB/s per lane. The PCI-SIG also expects the norm to evolve to reach 500&nbsp;MB/s, as in PCI Express 2.0. An example of the uses of Cabled PCI Express is a metal enclosure, containing a number of PCIe slots and PCIe-to-ePCIe adapter circuitry. This device would not be possible had it not been for the ePCIe specification.

==== PCI Express OCuLink <span class="anchor" id="OCULINK"></span> ====
''OCuLink'' (standing for "optical-copper link", as ''Cu'' is the [[Symbol (chemistry)|chemical symbol]] for [[copper]]) is an extension for the "cable version of PCI Express". Version 1.0 of OCuLink, released in Oct 2015, supports up to 4 PCIe 3.0 lanes (3.9&nbsp;GB/s) over copper cabling; a [[fiber optic]] version may appear in the future.

The most recent version of OCuLink, OCuLink-2, supports up to 16&nbsp;GB/s (PCIe 4.0 x8)<ref name="OCuLink2" /> while the maximum bandwidth of a [[USB 4]] cable is 10GB/s.

While initially intended for use in PCIe interconnections in servers, OCuLink's popularity lies primarily in its use for laptops for the connection of powerful external GPU boxes, a more prevalent application.<ref name="6MiK5" />

=== Derivative forms ===
Numerous other form factors use, or are able to use, PCIe. These include:
* Low-height card
* [[ExpressCard]]: Successor to the [[PC Card]] form factor (with x1 PCIe and USB 2.0; hot-pluggable)
* PCI Express ExpressModule: A hot-pluggable modular form factor defined for servers and workstations
* [[XQD card]]: A PCI Express-based flash card standard by the [[CompactFlash Association]] with x2 PCIe
* [[CFexpress]] card: A PCI Express-based flash card by the CompactFlash Association in three form factors supporting 1 to 4 PCIe lanes
* SD card: The [[SD card#SD Express|SD Express]] bus, introduced in version 7.0 of the SD specification uses a x1 PCIe link
* [[Switched Mezzanine Card|XMC]]: Similar to the [[Common Mezzanine Card|CMC]]/[[PCI Mezzanine Card|PMC]] form factor (VITA 42.3)
* [[Advanced Telecommunications Computing Architecture|AdvancedTCA]]: A complement to [[CompactPCI]] for larger applications; supports serial based backplane topologies
* [[Advanced Mezzanine Card|AMC]]: A complement to the [[Advanced Telecommunications Computing Architecture|AdvancedTCA]] specification; supports processor and I/O modules on ATCA boards (x1, x2, x4 or x8 PCIe).
* [[FeaturePak]]: A tiny expansion card format (43{{nbsp}}mm × 65&nbsp;mm) for embedded and small-form-factor applications, which implements two x1 PCIe links on a high-density connector along with USB, I2C, and up to 100 points of I/O
* [[Universal IO]]: A variant from [[Supermicro|Super Micro Computer]] Inc designed for use in low-profile rack-mounted chassis.<ref name="tNP5L" /> It has the connector bracket reversed so it cannot fit in a normal PCI Express socket, but it is pin-compatible and may be inserted if the bracket is removed.
* [[M.2]] (formerly known as NGFF)
* [[M-PCIe]] brings PCIe 3.0 to mobile devices (such as tablets and smartphones), over the [[M-PHY]] physical layer.<ref name="osiit" /><ref name="PoRghEr" />
* [[U.2]] (formerly known as SFF-8639)
* [[SlimSAS]]

The PCIe slot connector can also carry protocols other than PCIe. Some [[List of Intel chipsets|9xx series Intel chipsets]] support [[Serial Digital Video Out]], a proprietary technology that uses a slot to transmit video signals from the host CPU's [[Intel GMA|integrated graphics]] instead of PCIe, using a supported add-in.

The PCIe transaction-layer protocol can also be used over some other interconnects, which are not electrically PCIe:
* [[Thunderbolt (interface)|Thunderbolt]]: A royalty-free <!-- as of Thunderbolt 3 --> interconnect standard by Intel that combines [[DisplayPort]] and PCIe protocols in a form factor compatible with [[Mini DisplayPort]]. Thunderbolt 3.0 also combines USB 3.1 and uses the [[USB-C]] form factor as opposed to Mini DisplayPort.
* [[USB4]]