Editing PIC microcontrollers (section)

===PIC10 and PIC12===
{{Further|topic=this family of microcontrollers|PIC instruction listings#Baseline core devices (12-bit)}}
These devices feature a 12-bit wide code memory, a 32-byte register file, and a tiny two level deep call stack. They are represented by the PIC10 series, as well as by some PIC12 and PIC16 devices. Baseline devices are available in 6-pin to 40-pin packages.

Generally the first 7 to 9 bytes of the register file are special-purpose registers, and the remaining bytes are general purpose RAM. Pointers are implemented using a register pair: after writing an address to the FSR (file select register), the INDF (indirect f) register becomes an alias for the addressed register. If banked RAM is implemented, the bank number is selected by the high 3 bits of the FSR. This affects register numbers 16–31; registers 0–15 are global and not affected by the bank select bits.

Because of the very limited register space (5 bits), 4 rarely read registers were not assigned addresses, but written by special instructions (<code>OPTION</code> and <code>TRIS</code>).

The ROM address space is 512 and may only specify addresses in the first half of each 512-word page. That is, the CALL instruction specifies the low 9 bits of the address, but only the low 8 bits of that address are a parameter of the instruction, while the 9th bit (bit 8) is implicitly specified as 0 by the CALL instruction itself.

Lookup tables are implemented using a computed <code>GOTO</code> (assignment to PCL register) into a table of <code>RETLW</code> instructions. RETLW performs a subroutine return and simultaneously loads the W register with an 8-bit immediate constant that is part of the instruction.

This "baseline core" does ''not'' support [[interrupt]]s; all [[Input/output|I/O]] must be [[Polling (computer science)|polled]]. There are some "enhanced baseline" variants with interrupt support and a four-level call stack.

PIC10F32x devices feature a mid-range 14-bit wide code memory of 256 or 512 words, a 64-byte SRAM register file, and an 8-level deep hardware stack. These devices are available in 6-pin SMD and 8-pin DIP packages (with two pins unused). One input only and three I/O pins are available. A complex set of interrupts are available. Clocks are an internal calibrated high-frequency oscillator of 16&nbsp;MHz with a choice of selectable speeds via software and a 31&nbsp;kHz low-power source.